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    Method of forming diffusion barrier for copper interconnects
    41.
    发明授权
    Method of forming diffusion barrier for copper interconnects 有权
    形成铜互连的扩散阻挡层的方法

    公开(公告)号：US06342444B1

    公开(公告)日：2002-01-29

    申请号：US09522595

    申请日：2000-03-10

    Applicant: Kazuyuki Higashi ,  Noriaki Matsunaga ,  Hiroshi Toyoda ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Hisashi Kaneko

    Inventor： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Hiroshi Toyoda ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Hisashi Kaneko

    IPC: H01L214763

    CPC classification number: H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A TiN film is selectively formed as a barrier layer on a Cu metal layer by selective removal of a Ti metal layer on the Si metal layer after the following steps of selectively forming a Si metal layer as an etching mask on an insulation film, forming a trench pattern by selective removal of the insulation film using the Si metal layer, forming a Cu metal layer in the trench pattern with the Si metal layer remained, forming the Ti metal layer on the Si metal layer and the Cu metal layer as a barrier material with a different kind of eutectic reaction with Cu from the reaction with the etching mask by heat-treatment in an atmosphere of nitrogen, and selectively nitriding the Ti metal layer on the Cu metal layer by heat-treatment of the Ti metal layer in an atmosphere of nitrogen.

    Abstract translation: 通过在绝缘膜上选择性地形成Si金属层作为蚀刻掩模的以下步骤之后，通过选择性地除去Si金属层上的Ti金属层，在Cu金属层上选择性地形成TiN膜作为阻挡层，形成 沟槽图案，通过使用Si金属层选择性去除绝缘膜，在沟槽图案中形成具有Si金属层的Cu金属层，在Si金属层上形成Ti金属层，将Cu金属层形成为阻挡材料 在氮气气氛中通过热处理与与蚀刻掩模的反应与Cu的不同种类的共晶反应，并且通过在气氛中热处理Ti金属层来选择性地氮化Cu金属层上的Ti金属层 的氮气。

    Phase shifting mask and method of manufacturing the same
    42.
    发明授权
    Phase shifting mask and method of manufacturing the same 失效
    相移掩模及其制造方法

    公开(公告)号：US5958630A

    公开(公告)日：1999-09-28

    申请号：US953

    申请日：1997-12-30

    Applicant: Koji Hashimoto ,  Tetsuo Matsuda

    Inventor： Koji Hashimoto ,  Tetsuo Matsuda

    IPC: G03F1/30 ,  H01L21/027 ,  G03F9/00

    CPC classification number: G03F1/30

    Abstract: The present invention is directed to the prevention of a decrease in the resolution of a film shifter-type alternating phase shifting mask, and the complexity of the mask forming step, and discusses the structure of a novel alternating phase shifting mask, and a novel manufacturing method which does not require the etching for forming a shifter. To achieve this object, hydrogen silsesquioxane (flowable oxide (FOX)) is used as the material for the phase shifter. The optical characteristics of this film are very close to those of a quartz substrate, and the property that the in-surface variation (.+-.3 .sigma.) of the thickness is 1% or less, is close to that of SOG (Spin On Glass). The most advantageous aspect of the FOX being used for the mask manufacturing process is that, since the FOX film is etched at the same time as the resist development, with the alkaline developing solution used for etching the resist, there is no need to provide a particular step for etching the shifter.

    Abstract translation: 本发明涉及防止膜移位器型交替相移掩模的分辨率降低以及掩模形成步骤的复杂性，并且讨论了新颖的交替相移掩模的结构和新颖的制造 方法，其不需要用于形成移位器的蚀刻。 为了实现该目的，使用氢倍半硅氧烷（可流动氧化物（FOX））作为移相器的材料。 该膜的光学特性非常接近于石英基板，其厚度的面内变化（+/- 3西格玛）为1％以下，与SOG接近（Spin On 玻璃）。 用于掩模制造工艺的FOX最有利的方面是，由于与抗蚀剂显影同时蚀刻FOX膜，所以使用用于蚀刻抗蚀剂的碱性显影液，不需要提供 蚀刻移位器的特定步骤。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    45.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20130009241A1

    公开(公告)日：2013-01-10

    申请号：US13423138

    申请日：2012-03-16

    Applicant: Tetsuo MATSUDA

    Inventor： Tetsuo MATSUDA

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7802 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7813

    Abstract: According to one embodiment, a semiconductor device includes a drain layer, a drift, a base, a source region, a plurality of gates provided on the drift region, the base, and the source region, and arranged in a manner spaced apart from each other, a first interlayer insulating film arranged between the plurality of gates on the source region, a gate interconnection film provided on the first interlayer insulating film and the gate, a second interlayer insulating film provided on the gate interconnection film, an inetconnection film provided on the second interlayer insulating film and connected in common to the source region, the interconnection film filling the contact hole provided between each of the gates in the second interlayer insulating film, the gate interconnection film and the first interlayer insulating film and an insulating film arranged between the gate interconnection film and the interconnection film in the contact hole.

    Abstract translation: 根据一个实施例，半导体器件包括漏极层，漂移层，基极，源极区域，设置在漂移区域上的多个栅极，基极和源极区域，并以与每个栅极间隔开的方式布置 另外，设置在源区上的多个栅极之间的第一层间绝缘膜，设置在第一层间绝缘膜和栅极上的栅极互连膜，设置在栅极互连膜上的第二层间绝缘膜，设置在栅极互连膜上的互连膜 所述第二层间绝缘膜与所述源极区域共同连接，所述互连膜填充设置在所述第二层间绝缘膜中的每个栅极之间的接触孔，所述栅极互连膜和所述第一层间绝缘膜以及布置在所述第二层间绝缘膜之间的绝缘膜 门互连膜和接触孔中的互连膜。

    Plating method
    47.
    发明授权
    Plating method 失效
    电镀方法

    公开(公告)号：US07575664B2

    公开(公告)日：2009-08-18

    申请号：US11135328

    申请日：2005-05-24

    Applicant: Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

    Inventor： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

    IPC: C25D21/12

    CPC classification number: C25D5/16 ,  C25D5/02 ,  C25D5/06 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

    Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

    Abstract translation: 对形成在具有凹陷图案的基板上的导电层施加阴极电位。 将与阳极电接触的电镀溶液供给到导电层，以在导电层上形成镀膜。 此时，通过使包含电镀液的浸渍部件面对导电层而供给电镀液。 由于电镀溶液滞留在凹陷中，所以与基板的上表面相比，供给电镀液的量较多，因此抑制了镀膜的镀覆速度。 因此，可以在诸如凹槽或孔的凹陷中优先地形成镀膜。

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