公开(公告)号：US08163601B2

公开(公告)日：2012-04-24

申请号：US12894105

申请日：2010-09-29

Applicant: Yuping Gong ,  Yan Xun Xue

Inventor： Yuping Gong ,  Yan Xun Xue

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/49562 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0346 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/3701 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/83191 ,  H01L2224/8485 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/01028 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.

Abstract translation: 一种制造芯片暴露半导体封装的方法，包括以下步骤：在晶片上的每个芯片的正面上电镀多个电极; 研磨晶片的背面并沉积后金属，然后分离每个芯片; 安装具有粘附在引线框架的多个桨叶的前面上的电镀电极的芯片; 将胶带粘附在背面金属上并用模塑料包封; 移除带子并穿过引线框架和模塑料形成多个封装的半导体器件。

公开(公告)号：US20120025360A1

公开(公告)日：2012-02-02

申请号：US12846034

申请日：2010-07-29

Applicant: Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

Inventor： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L21/56 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40248 ,  H01L2224/40249 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.

Abstract translation: 半导体封装包括引线框架，还包括芯片载体和与芯片载体相邻的多个引脚。 从芯片载体的上表面开放的多个槽将芯片载体部分地分成多个芯片安装区域。 去除凹槽的底部以完全隔离每个芯片安装区域，其中移除的凹槽的底部的宽度小于凹槽的宽度。 在一个实施例中，凹槽位于芯片载体和引脚之间，其中凹槽的底部被移除以将引脚与芯片载体隔离开，其中移除的凹槽的底部的宽度小于凹槽的宽度 。

公开(公告)号：US20110024884A1

公开(公告)日：2011-02-03

申请号：US12693446

申请日：2010-01-26

Applicant: Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

Inventor： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/84

Abstract: A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.

Abstract translation: 用于功率转换器应用的半导体封装包括低边MOSFET芯片和高边MOSFET芯片。 半导体封装可以进一步包围电容器，而电容器可以是分立元件或芯片级与低边MOSFET的集成元件。 半导体封装还可以包括PIC芯片，以在半导体芯片组件封装级别上提供完整的功率转换器。

公开(公告)号：US09391005B2

公开(公告)日：2016-07-12

申请号：US14033140

申请日：2013-09-20

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC: H01L23/495

CPC classification number: H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/16245 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

Abstract translation: 功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。 桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。

公开(公告)号：US20150249045A1

公开(公告)日：2015-09-03

申请号：US14194502

申请日：2014-02-28

Applicant: Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

Inventor： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

IPC: H01L23/495 ,  H01L23/29 ,  H01L21/78

CPC classification number: H01L23/49551 ,  H01L21/561 ,  H01L21/78 ,  H01L23/043 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/73253

Abstract: A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units.

Abstract translation: 一种功率半导体器件的制备方法，包括：提供包含多个芯片安装单元的引线框架，每个芯片安装单元的模板的一个侧边缘向上弯曲并向上延伸，并且一个引线连接到所述芯片安装单元的弯曲侧边缘 模具桨，并且在与模桨相反的方向上延伸; 将半导体芯片附接到所述管芯焊盘的顶表面; 在半导体芯片的前面的每个电极上形成金属凸块，每个金属凸块的顶端从引线的顶表面的平面突出; 加热金属凸块并通过压板压制每个金属凸块的顶端，该压板形成与引线顶表面齐平的平坦顶端表面; 并切割引线框架以分离各个芯片安装单元。

公开(公告)号：US08981539B2

公开(公告)日：2015-03-17

申请号：US13913717

申请日：2013-06-10

Applicant: Yan Xun Xue ,  Hamza Yilmaz

Inventor： Yan Xun Xue ,  Hamza Yilmaz

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/34 ,  H01L23/12 ,  H01L23/02

CPC classification number: H01L23/49568 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/17 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.

Abstract translation: 功率半导体器件包括引线框单元，控制管芯，第一MOSFET管芯和第二MOSFET管芯，其中引线框架单元至少包括用于安装第一和第二MOSFET管芯的管芯焊盘，第一管脚和第二管脚 引脚，用于连接到第一和第二MOSFET管芯的顶部电极，第一行载体引脚和第二排载体引脚，分别与第一和第二引脚成对设置，用于控制管芯安装在其上。

公开(公告)号：US20140361419A1

公开(公告)日：2014-12-11

申请号：US13913717

申请日：2013-06-10

Applicant: Yan Xun Xue ,  Hamza Yilmaz

Inventor： Yan Xun Xue ,  Hamza Yilmaz

IPC: H01L23/495

CPC classification number: H01L23/49568 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/17 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.

Abstract translation: 功率半导体器件包括引线框单元，控制管芯，第一MOSFET管芯和第二MOSFET管芯，其中引线框架单元至少包括用于安装第一和第二MOSFET管芯的管芯焊盘，第一管脚和第二管脚 引脚，用于连接到第一和第二MOSFET管芯的顶部电极，第一行载体引脚和第二排载体引脚，分别与第一和第二引脚成对设置，用于控制管芯安装在其上。

公开(公告)号：US20140361418A1

公开(公告)日：2014-12-11

申请号：US13913183

申请日：2013-06-07

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L23/495

CPC classification number: H01L23/4951 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

Abstract translation: 本发明涉及倒装芯片的半导体封装以及制造半导体封装的方法。 半导体芯片包括金属氧化物半导体场效应晶体管。 在包括第一基底，第二基底和第三基底的裸片上，在第一基底和第二基底的顶表面上进行半蚀刻或冲孔，以获得多个凹槽，该凹槽将第一基底 进入包括多个第一连接区域的多个区域，并且将第二基座的顶表面分成包括至少第二连接区域的多个区域。 半导体芯片在第一连接区域和第二连接区域处连接到管芯焊盘。

公开(公告)号：US08865523B2

公开(公告)日：2014-10-21

申请号：US13833341

申请日：2013-03-15

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC: H01L23/495 ,  H01L21/78

CPC classification number: H01L23/49562 ,  H01L21/561 ,  H01L21/78 ,  H01L23/06 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49568 ,  H01L2224/32245 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

Abstract translation: 一种制造半导体封装器件的方法包括将引线框架安装在模制半导体芯片的底部，该底部具有覆盖半导体芯片的顶面的第一塑料封装体，用第二塑料封装体封装引线框和半导体芯片 导电接触体的顶表面电连接到半导体芯片的顶表面上的电极，并暴露在组件结构的顶表面上的导电焊盘，以通过导电接触体提供与电极的外部电连接。

公开(公告)号：US20140141567A1

公开(公告)日：2014-05-22

申请号：US13678847

申请日：2012-11-16

Applicant: Lei Shi ,  Yan Xun Xue ,  Yuping Gong

Inventor： Lei Shi ,  Yan Xun Xue ,  Yuping Gong

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/4832 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.

Abstract translation: 公开了专门用于倒装芯片垂直功率器件的封装半导体器件的制备方法。 在这些方法中，将垂直半导体芯片倒装芯片连接到引线框架，然后用塑料包装材料封装。 然后将封装的芯片变薄到预定厚度。 通过蚀刻至少连接的引线框架的底部部分，形成连接芯片与外部电路的接触端子。