公开(公告)号：US20050270871A1

公开(公告)日：2005-12-08

申请号：US11198225

申请日：2005-08-08

申请人： Yasushige Ogawa ,  Yoshiyuki Ishida ,  Masato Matsumiya

发明人： Yasushige Ogawa ,  Yoshiyuki Ishida ,  Masato Matsumiya

IPC分类号： H01L27/04 ,  G01R31/3167 ,  H01L21/822 ,  H03M1/10 ,  H03M1/66 ,  G11C7/00

CPC分类号： H03M1/1019 ,  G01R31/3167 ,  H03M1/66

摘要： It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4. Consequently, the analog signal can be adjusted as analog value without being outputted outside and an adjustment test can be carried out with a simple tester device and according to a simple test method accurately and rapidly.

摘要翻译： 本发明旨在提供一种半导体集成电路器件的半导体集成电路器件和调整方法，该半导体集成电路器件能够调整从内置的模拟信号产生部分输出的模拟信号而不将其输出为模拟值。 从输入调整信号AD的模拟信号生成部3输出模拟信号AOUT。 模拟信号AOUT被输入到判断部分1，在判定部分1中，以预定值进行比较和判断，然后输出判断信号JG。 判断信号JG作为内部信号作用于预定信号存储部分4，并且调节信号AD被取出到预定信号存储部分4.此外，判断信号JG通过外部端子T 2作为数字信号输出， 外部测试器装置获取调整信号并将获取的调节信号存储在预定信号存储部分4中。因此，可以将模拟信号调整为模拟值而不输出到外部，并且可以使用简单的测试装置进行调整测试， 根据简单的测试方法准确快速。

公开(公告)号：US06700437B1

公开(公告)日：2004-03-02

申请号：US09642937

申请日：2000-08-22

申请人： Yasushige Ogawa ,  Yoshiyuki Ishida

发明人： Yasushige Ogawa ,  Yoshiyuki Ishida

IPC分类号： G05F110

CPC分类号： G11C29/12005 ,  G11C7/1006 ,  G11C7/22 ,  G11C29/02 ,  G11C2029/0401 ,  G11C2029/5006 ,  G11C2207/2227

摘要： A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.

摘要翻译： 半导体器件包括逻辑电路和宏电路。 宏电路包括消耗直流（DC）电路。 为了节省电力并允许测试，可以通过停止信号停止由电流消耗电路消耗的DC，从而停止宏电路的操作。 宏电路可以重启或恢复正常工作模式，而不会由于宏电路停止而引起误差。

公开(公告)号：US06269033B1

公开(公告)日：2001-07-31

申请号：US09480619

申请日：2000-01-10

申请人： Yoshiyuki Ishida ,  Yasushige Ogawa

发明人： Yoshiyuki Ishida ,  Yasushige Ogawa

IPC分类号： G11C702

CPC分类号： G11C29/848

摘要： A semiconductor memory device, such as a SDRAM, includes input/output data line pairs, data bus line pairs, and a redundancy data bus line pair. The input/output data line pairs are connected to a corresponding one of the data bus line pairs and an adjacent one of the data bus line pairs via redundancy shift switches, with a last one of the input/output data line pairs being connected to a last one fo the data bus line pairs and the redundancy data bus line pair. Sense buffers and write amplifiers are connected between each of the data bus line pairs and the redundancy data line pair. The shift switches are located closer to the input/output data line pairs than the sense buffers and the write amplifiers so that data read from the memory cells is less effected by the on resistance and the parasitic capacitance of the switches. When the switches are located closer to the data bus lines than the sense buffers and the write amplifiers are, the switches effect the data signals of data read from the memory cells.

摘要翻译： 诸如SDRAM的半导体存储器件包括输入/​​输出数据线对，数据总线线对和冗余数据总线对。 输入/输出数据线对通过冗余移位开关连接到数据总线线对中的相应一条数据总线线对，其中最后一条输入/输出数据线对连接到 最后一个数据总线线对和冗余数据总线对。 读数缓冲器和写放大器连接在每个数据总线线对和冗余数据线对之间。 移位开关位于比读出缓冲器和写入放大器更靠近输入/输出数据线对的位置，使得从存储器单元读取的数据不受开关的导通电阻和寄生电容的影响。 当开关位于比读取缓冲器和写入放大器更靠近数据总线时，开关影响从存储器单元读取的数据的数据信号。

公开(公告)号：US5835408A

公开(公告)日：1998-11-10

申请号：US985714

申请日：1997-12-05

申请人： Takao Akaogi ,  Yasushige Ogawa ,  Tatsuya Kajita ,  Hisayoshi Watanabe ,  Minoru Yamashita

发明人： Takao Akaogi ,  Yasushige Ogawa ,  Tatsuya Kajita ,  Hisayoshi Watanabe ,  Minoru Yamashita

IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C29/00 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  G11C16/06

CPC分类号： H01L27/11526 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C29/846 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11543

摘要： A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

公开(公告)号：US5631597A

公开(公告)日：1997-05-20

申请号：US445103

申请日：1995-05-19

申请人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/21 ,  G05F1/10

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C5/145 ,  H03K19/018521 ,  H03K19/215 ,  H03K3/356147 ,  H03K3/356165

摘要： A negative-voltage circuit for realizing a flash memory is installed independently and is applied selectively to word lines in response to signals sent from row decoders. Row decoders for specifying word lines need not be installed in the negative voltage circuit. The negative circuit can therefore be reduced in scale.

摘要翻译： 独立地安装用于实现闪速存储器的负电压电路，并响应于从行解码器发送的信号而选择性地对字线施加。 用于指定字线的行解码器不需要安装在负电压电路中。 因此，可以减小负电路的规模。

公开(公告)号：US5519652A

公开(公告)日：1996-05-21

申请号：US158796

申请日：1993-12-01

申请人： Sinsuke Kumakura ,  Yasushige Ogawa ,  Takao Akaogi ,  Tetsuya Chida

发明人： Sinsuke Kumakura ,  Yasushige Ogawa ,  Takao Akaogi ,  Tetsuya Chida

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/26 ,  G11C16/28 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50 ,  G11C29/56 ,  G11C11/34

CPC分类号： G11C29/50016 ,  G11C16/26 ,  G11C16/28 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5006

摘要： A semiconductor memory has a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a differential sense amplifier, and load transistors. Each of the memory cells is a MIS transistor formed at each intersection of the word and bit lines. The threshold voltage of the MIS transistor is externally electrically controllable. The differential sense amplifier senses data stored in a selected memory cell located at an intersection of selected word and bit lines. A control pulse signal is applied to the gates of the load transistors, to bias the bit lines. The pulse width of the control pulse signal is a minimum essential to read data out of the selected memory cell. The control pulse signal controls the switching of the load transistors, to shorten a period during which a stress voltage is continuously applied to the drains of unselected memory cells that are connected to the bit line to which the selected memory cell is connected.

摘要翻译： 半导体存储器具有多个字线，多个位线，多个存储单元，差分读出放大器和负载晶体管。 每个存储单元是形成在字和位线的每个交叉处的MIS晶体管。 MIS晶体管的阈值电压是外部电可控的。 差分读出放大器感测存储在位于选定字和位线的交叉点处的选定存储单元中的数据。 控制脉冲信号施加到负载晶体管的栅极，以偏置位线。 控制脉冲信号的脉冲宽度是从所选存储单元读出数据所必需的最小值。 控制脉冲信号控制负载晶体管的切换，以缩短连续施加到与所选存储单元连接的位线的未选择存储单元的漏极的应力电压的周期。

公开(公告)号：US08174282B2

公开(公告)日：2012-05-08

申请号：US12576670

申请日：2009-10-09

申请人： Kiyonaga Fujii ,  Yasushige Ogawa

发明人： Kiyonaga Fujii ,  Yasushige Ogawa

IPC分类号： G01R31/02 ,  G01R31/28

CPC分类号： G01R31/2621 ,  G01R31/2884 ,  G01R31/3008 ,  G01R31/3012

摘要： A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at least one P-channel MOS transistor which is coupled to a high potential power supply and which is normally inactivated and generates a first leak current, at least one N-channel MOS transistor which is coupled between a low potential power and at least the one P-channel MOS transistor and which is normally inactivated and generates a second leak current, and a detector which detects a potential generated at a node between the at least one P-channel MOS transistor and the at least one N-channel MOS transistor in accordance with the first and second leak currents.

摘要翻译： 一种泄漏电流检测电路，其提高了在不增加电路规模的情况下检测MOS晶体管中的漏电流的精度。 泄漏电流检测电路包括耦合到高电位电源的至少一个P沟道MOS晶体管，其通常是非激活的并且产生第一漏电流，至少一个N沟道MOS晶体管耦合在低电位 功率和至少一个P沟道MOS晶体管，并且其通常被非激活并产生第二漏电流;以及检测器，其检测在所述至少一个P沟道MOS晶体管和所述至少一个N之间的节点处产生的电位 - 沟道MOS晶体管，根据第一和第二漏电流。

公开(公告)号：US20110012672A1

公开(公告)日：2011-01-20

申请号：US12835732

申请日：2010-07-13

申请人： Yasushige OGAWA

发明人： Yasushige OGAWA

IPC分类号： G05F1/10

CPC分类号： G05F3/205

摘要： A body-bias voltage controller includes: a plurality of transistors at least one of which is supplied with a body-bias voltage; a monitor circuit to detect voltage characteristics of the plurality of transistors and to output a indicator signal; and a body-bias voltage generator to generate the body-bias voltage based upon the indicator signal.

摘要翻译： 体偏置电压控制器包括：多个晶体管，其中至少一个具有体偏置电压; 监视电路，用于检测多个晶体管的电压特性并输出指示信号; 以及体偏置电压发生器，用于基于指示信号产生体偏置电压。

公开(公告)号：US20100052727A1

公开(公告)日：2010-03-04

申请号：US12614713

申请日：2009-11-09

申请人： Hiroyuki SUGAMOTO ,  Hidetoshi Tanaka ,  Yasushige Ogawa

发明人： Hiroyuki SUGAMOTO ,  Hidetoshi Tanaka ,  Yasushige Ogawa

IPC分类号： G01R31/28

CPC分类号： G11C8/08 ,  G01R31/31701 ,  G11C29/34

摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carry out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will resent a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

摘要翻译： 本发明提供一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地进行老化应力试验。 具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。 脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号重新发出。 同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。

公开(公告)号：US07663392B2

公开(公告)日：2010-02-16

申请号：US12112782

申请日：2008-04-30

申请人： Hiroyuki Sugamoto ,  Hidetoshi Tanaka ,  Yasushige Ogawa

发明人： Hiroyuki Sugamoto ,  Hidetoshi Tanaka ,  Yasushige Ogawa

IPC分类号： G01R31/28 ,  G11C7/00

CPC分类号： G11C8/08 ,  G01R31/31701 ,  G11C29/34

摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

摘要翻译： 本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。 具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。 脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。 同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。