公开(公告)号：US20120194244A1

公开(公告)日：2012-08-02

申请号：US13166051

申请日：2011-06-22

Applicant: Yong Hoon KIM ,  Chun Seok JEONG

Inventor： Yong Hoon KIM ,  Chun Seok JEONG

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: A semiconductor memory apparatus may comprise a duty cycle correction circuit configured to perform a duty correction operation with respect to an input clock signal when a delay locked signal is activated, and perform the duty correction operation with respect to the input signal when a precharge signal is activated, to generate a corrected clock signal.

Abstract translation: 半导体存储装置可以包括占空比校正电路，其被配置为当延迟锁定信号被激活时对输入时钟信号执行占空比校正操作，并且当预充电信号为...时，对输入信号执行占空比校正操作 激活，以产生校正的时钟信号。

公开(公告)号：US20120126431A1

公开(公告)日：2012-05-24

申请号：US13278620

申请日：2011-10-21

Applicant: Yong-Hoon KIM ,  So-Young LIM ,  In-Ho CHOI

Inventor： Yong-Hoon KIM ,  So-Young LIM ,  In-Ho CHOI

IPC: H01L23/538

CPC classification number: H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00014

Abstract: A semiconductor package having improved EMI and crosstalk characteristics is provided. The semiconductor package includes a semiconductor package including a substrate, at least one first semiconductor chip formed on a top surface of the substrate and electrically connected to the substrate, and at least one second semiconductor chip formed on a top surface of the first semiconductor chip and electrically connected to the first semiconductor chip, wherein first and second conductive layers are formed on the top surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the first conductive layer and the second conductive layer are connected to a ground portion.

Abstract translation: 提供了具有改善的EMI和串扰特性的半导体封装。 半导体封装包括半导体封装，其包括衬底，形成在衬底的顶表面上并电连接到衬底的至少一个第一半导体芯片，以及形成在第一半导体芯片的顶表面上的至少一个第二半导体芯片，以及 电连接到第一半导体芯片，其中第一和第二导电层分别形成在第一半导体芯片和第二半导体芯片的顶表面上，并且第一导电层和第二导电层连接到接地部分。

公开(公告)号：US20110316119A1

公开(公告)日：2011-12-29

申请号：US13168111

申请日：2011-06-24

Applicant: Yong-hoon KIM ,  Yeong-jun Cho ,  Ji-hyun Lee ,  Hee-seok Lee

Inventor： Yong-hoon KIM ,  Yeong-jun Cho ,  Ji-hyun Lee ,  Hee-seok Lee

IPC: H01L23/485

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/228 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/642 ,  H01L24/16 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01038 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1902 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Provided is a semiconductor package including a de-coupling capacitor. The semiconductor package includes a substrate, on an upper surface of which a semiconductor chip is mounted; a plurality of first conductive bumps that are disposed on a lower surface of the substrate and that electrically connect the substrate to an external device; and a de-coupling capacitor that is disposed on the lower surface of the substrate and includes an electrode portion and at least one dielectric layer, wherein the electrode portion of the de-coupling capacitor includes second conductive bumps that electrically connect the substrate to an external device.

Abstract translation: 提供了包括去耦电容器的半导体封装。 半导体封装包括：衬底，其上表面安装有半导体芯片; 多个第一导电凸块，其设置在所述基板的下表面上，并将所述基板电连接到外部装置; 以及解耦电容器，其设置在所述基板的下表面上并且包括电极部分和至少一个电介质层，其中所述解耦电容器的电极部分包括将所述基板电连接到外部的第二导电凸块 设备。

公开(公告)号：US20110304763A1

公开(公告)日：2011-12-15

申请号：US13095155

申请日：2011-04-27

Applicant: Mi-Na Choi ,  Kyoung-Sei Choi ,  Hee-Seok Lee ,  Yong-Hoon Kim ,  Hee-Jung Hwang ,  Se-Ran Bae

Inventor： Mi-Na Choi ,  Kyoung-Sei Choi ,  Hee-Seok Lee ,  Yong-Hoon Kim ,  Hee-Jung Hwang ,  Se-Ran Bae

IPC: H04N5/225 ,  H01L31/0216

CPC classification number: H04N5/2253

Abstract: An image sensor chip, a camera module, and devices incorporating the image sensor chip and camera module include a light receiving unit on which light is incident, a logic unit provided to surround the light receiving unit, and an electromagnetic wave shielding layer formed on the logic unit and not formed on the light receiving unit.

Abstract translation: 图像传感器芯片，相机模块以及包含图像传感器芯片和相机模块的装置包括光入射的光接收单元，围绕光接收单元的逻辑单元和形成在该光接收单元上的电磁波屏蔽层 逻辑单元，并且不形成在光接收单元上。

公开(公告)号：US20110156771A1

公开(公告)日：2011-06-30

申请号：US12648795

申请日：2009-12-29

Applicant: Yong-Hoon Kim ,  Hyun-Woo Lee

Inventor： Yong-Hoon Kim ,  Hyun-Woo Lee

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/0816

Abstract: A semiconductor device includes: an internal clock signal generation unit configured to receive an external clock signal and to generate an internal clock signal in response to a control signal; and a monitoring unit configured to monitor environmental elements reflected in a circuit response to the control signal.

Abstract translation: 半导体器件包括：内部时钟信号生成单元，被配置为接收外部时钟信号并响应于控制信号产生内部时钟信号; 以及监视单元，被配置为监视反映在对所述控制信号的电路响应中的环境因素。

公开(公告)号：US07873822B2

公开(公告)日：2011-01-18

申请号：US11797985

申请日：2007-05-09

Applicant: Yong-Hoon Kim ,  Yun-Tae Lee ,  Sung-Up Choi

Inventor： Yong-Hoon Kim ,  Yun-Tae Lee ,  Sung-Up Choi

IPC: G06F15/177

CPC classification number: G06F9/4401

Abstract: An electronic information system comprises an external storage device and an application processor. The external storage device stores boot code and the application processor is adapted to receive the boot code from the external storage device and to perform a system booting operation during a power-up operation by executing the boot code.

Abstract translation: 电子信息系统包括外部存储装置和应用处理器。 外部存储装置存储引导代码，并且应用处理器适于从外部存储设备接收引导代码，并且在上电操作期间通过执行引导代码执行系统引导操作。

公开(公告)号：US07843223B1

公开(公告)日：2010-11-30

申请号：US12494748

申请日：2009-06-30

Applicant: Yong-Hoon Kim

Inventor： Yong-Hoon Kim

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/018521

Abstract: A semiconductor device includes a buffer unit configured to include first and second buffers, connected to each other in a cross-coupled manner, to receive a reference voltage and to buffer an input signal applied to the first and second buffers based on the reference voltage to drive an output terminal with a current-driving capacity; and a drive power adjustor configured to adjust the current-driving capacity depending on a level of a power supply voltage applied to the buffering unit.

Abstract translation: 半导体器件包括缓冲单元，其被配置为包括以交叉耦合方式彼此连接的第一和第二缓冲器，以接收基准电压，并且基于参考电压缓冲施加到第一和第二缓冲器的输入信号 驱动具有电流驱动能力的输出端子; 以及驱动电力调整器，被配置为根据施加到缓冲单元的电源电压的电平来调整电流驱动能力。

公开(公告)号：US20090313403A1

公开(公告)日：2009-12-17

申请号：US12167574

申请日：2008-07-03

Applicant: Seong Ho Cheong ,  Yong Hoon Kim

Inventor： Seong Ho Cheong ,  Yong Hoon Kim

IPC: G06F13/38

CPC classification number: G06F21/83 ,  G06F21/606

Abstract: Provided is a method of securing a Universal Serial Bus (USE) keyboard. According to the method, a keyboard security operation is performed at a host controller driver level, which is one level lower than a USE hub driver level. Thus, it is possible to rapidly and effectively prevent a malicious program from leaking information input from a keyboard that is in communication with a main frame and transfers data via a USB.

Abstract translation: 提供了一种固定通用串行总线（USE）键盘的方法。 根据该方法，在主机控制器驱动器级别执行键盘安全操作，该级别低于USE集线器驱动器级别的一级。 因此，可以快速有效地防止恶意程序泄漏从与主框架通信的键盘输​​入的信息，并经由USB传送数据。

公开(公告)号：US20090256598A1

公开(公告)日：2009-10-15

申请号：US12345761

申请日：2008-12-30

Applicant: Yong Hoon Kim

Inventor： Yong Hoon Kim

IPC: H03K17/22

CPC classification number: G11C7/20 ,  G11C5/143 ,  G11C5/147 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A power-up signal generator of a semiconductor memory apparatus includes a power-up signal generating unit that includes a MOS transistor having a gate receiving a divided voltage of an external supply voltage, the power-up signal generating unit determining a level of a power-up signal according to a turn-ON state of the MOS transistor, and a bulk bias voltage generating unit that applies a bulk bias voltage to a bulk of the MOS transistor to adjust a threshold voltage of the MOS transistor, wherein the bulk bias voltage varies according to a temperature of the semiconductor memory device.

Abstract translation: 一种半导体存储装置的上电信号发生器包括上电信号产生单元，该上电信号产生单元包括具有接收外部电源电压的分压的栅极的MOS晶体管，所述上电信号生成单元确定功率电平 - 根据MOS晶体管的导通状态的上电信号，以及体偏置电压产生单元，其向大量MOS晶体管施加体偏置以调节MOS晶体管的阈值电压，其中体偏置电压 根据半导体存储器件的温度而变化。

公开(公告)号：US07087843B2

公开(公告)日：2006-08-08

申请号：US10720282

申请日：2003-11-25

Applicant: Tadashi Ishii ,  Yong Hoon Kim ,  Atsushi Higashiura ,  Isamu Kobayashi

Inventor： Tadashi Ishii ,  Yong Hoon Kim ,  Atsushi Higashiura ,  Isamu Kobayashi

IPC: H01B3/30

CPC classification number: H01B3/301 ,  H01B3/306 ,  H01B3/307 ,  H01B3/427 ,  H01F27/2823 ,  H01F27/323 ,  Y10T428/31725 ,  Y10T428/31786

Abstract: A multilayer insulated wire having two or more extrusion-insulating layers provided on a conductor to coat the conductor, wherein at least one layer of the insulating layers is composed of a polyethersulfone resin (i), or a resin mixture (ii) made by blending: 100 parts by weight of a resin (A) of at least one selected from polyetherimide resins and polyethersulfone resins, and 10 parts by weight or more of a resin (B) of at least one selected from polycarbonate resins, polyarylate resins, polyester resins and polyamide resins; and wherein at least one layer other than the insulating layer composed of the resin (i) or resin mixture (ii) is provided as an outer layer to the insulating layer and is composed of a polyphenylenesulfide resin. A transformer can also have the mentioned multi-layered insulated wire.

Abstract translation: 一种多层绝缘线，其具有设置在导体上以涂覆导体的两个或更多个挤压绝缘层，其中至少一层绝缘层由聚醚砜树脂（i）或通过混合制成的树脂混合物（ii） ：100重量份选自聚醚酰亚胺树脂和聚醚砜树脂中的至少一种树脂（A）和10重量份以上选自聚碳酸酯树脂，聚芳酯树脂，聚酯树脂中的至少一种树脂（B） 和聚酰胺树脂; 并且其中除了由树脂（i）或树脂混合物（ii）组成的绝缘层以外的至少一层作为外层设置在绝缘层上，并由聚苯硫醚树脂构成。 变压器也可以具有上述的多层绝缘电线。