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    Idle phase exit prediction
    41.
    发明授权
    Idle phase exit prediction 有权
    空闲相位退出预测

    公开(公告)号：US09110671B2

    公开(公告)日：2015-08-18

    申请号：US13724599

    申请日：2012-12-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Srilatha Manne ,  William L Bircher ,  Mahdu S. S. Govindan ,  Michael J Schulte ,  Manish Arora

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

    Abstract: A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state.

    Abstract translation: 公开了一种基于先前预测退出低功率状态的方法和装置。 集成电路（IC）包括功能单元，其被配置为在操作期间在活动状态的间隔和空闲状态的间隔之间循环。 IC还包括电源管理单元，其被配置为响应于功能单元进入空闲状态而将功能单元置于低功率状态。 电源管理单元还被配置为在进入低功率之后的预定时间，预先使功能单元退出低功率状态。 预定时间基于在进入低功率状态之前进行的空闲状态持续时间的预测。 预测可以由预测单元基于功能单元处于空闲状态的间隔的持续时间的历史来生成。

    CONFIGURING PROCESSOR POLICIES BASED ON PREDICTED DURATIONS OF ACTIVE PERFORMANCE STATES
    42.
    发明申请
    CONFIGURING PROCESSOR POLICIES BASED ON PREDICTED DURATIONS OF ACTIVE PERFORMANCE STATES 审中-公开
    基于预期活跃绩效状态的配置处理者政策

    公开(公告)号：US20150186160A1

    公开(公告)日：2015-07-02

    申请号：US14146588

    申请日：2014-01-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne

    IPC: G06F9/445 ,  G06F11/34 ,  G06F12/08

    CPC classification number: G06F11/3423 ,  G06F1/3243 ,  G06F11/3452 ,  G06F12/0804 ,  G06F12/0864 ,  G06F2212/601 ,  Y02D10/152 ,  Y02D10/34 ,  Y02D50/20

    Abstract: Durations of active performance states of components of a processing system can be predicted based on one or more previous durations of an active state of the components. One or more entities in the processing system such as processor cores or caches can be configured based on the predicted durations of the active state of the components. Some embodiments configure a first component in a processing system based on a predicted duration of an active state of a second component of the processing system. The predicted duration is predicted based on one or more previous durations of an active state of the second component.

    Abstract translation: 可以基于组件的活动状态的一个或多个先前持续时间来预测处理系统的组件的主动性能状态的持续时间。 可以基于组件的活动状态的预测持续时间来配置处理系统中的一个或多个实体，例如处理器核心或高速缓存。 一些实施例基于处理系统的第二组件的活动状态的预测持续时间来配置处理系统中的第一组件。 基于第二组件的活动状态的一个或多个先前持续时间预测预测持续时间。

    Power management for heterogeneous computing systems
    43.
    发明授权
    Power management for heterogeneous computing systems 有权

    公开(公告)号：US10168762B2

    公开(公告)日：2019-01-01

    申请号：US14857574

    申请日：2015-09-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Can Hankendi ,  Manish Arora ,  Indrani Paul

    IPC: G06F1/32

    Abstract: A computing system includes a set of computing resources and a datastore to store information representing a corresponding idle power consumption metric and a corresponding peak power consumption metric for each computing resource of the set. The computing system further includes a controller coupled to the set of computing resources and the datastore. The controller is to configure the set of computing resources to meet a power budget constraint for the set based on the corresponding idle power consumption metric and the corresponding peak power consumption metric for each computing resource of the set.

    Decoupled selective implementation of entry and exit prediction for power gating processor components
    47.
    发明授权
    Decoupled selective implementation of entry and exit prediction for power gating processor components 有权
    电源门控处理器组件的进入和退出预测的去耦选择性实现

    公开(公告)号：US09507410B2

    公开(公告)日：2016-11-29

    申请号：US14310908

    申请日：2014-06-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Manish Arora ,  Indrani Paul

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3293 ,  G06N5/04 ,  Y02D10/171 ,  Y02D50/20

    Abstract: Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates of reliability of the exit prediction techniques.

    Abstract translation: 电源门控逻辑检测处理设备的组件转换到空闲状态。 响应于检测到转换，入口/出口功率门控逻辑基于入口预测技术的可靠性的估计，选择性地实现用于功率门控组件的一个或多个入口预测技术。 入口/出口电力门控逻辑还基于对退出预测技术的可靠性的估计，选择性地实现一个或多个退出预测技术以退出电力门控状态。

    EXPLOITING LIMITED CONTEXT STREAMS
    48.
    发明申请
    EXPLOITING LIMITED CONTEXT STREAMS 审中-公开
    有限上限流

    公开(公告)号：US20160224397A1

    公开(公告)日：2016-08-04

    申请号：US14610662

    申请日：2015-01-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Manish Arora ,  Can Hankendi ,  Syed Ali R. Jafri ,  Andrew G. Kegel

    IPC: G06F9/52 ,  G11C7/10 ,  G06F12/02 ,  G06F9/50 ,  G06F9/46

    CPC classification number: G06F9/485 ,  G06F12/0246 ,  G06F2212/7201 ,  H04W4/02 ,  H04W4/029 ,  H04W4/50

    Abstract: In one form, a data processing system includes volatile and non-volatile memory, a central processing unit, and at least one peripheral device. The central processing unit executes a selected one of a plurality of software applications as directed by an operating system by transferring the selected software application from the non-volatile memory to the volatile memory and executing instructions associated with the selected software application from the volatile memory. The at least one peripheral device includes a real-time clock for defining execution contexts for the plurality of software applications. The data processing system further includes a usage pattern analyzer adapted to store history information associated with an execution context for each of the plurality of software applications, and to use the history information to direct the operating system to take at least one action based on the history information.

    Abstract translation: 在一种形式中，数据处理系统包括易失性和非易失性存储器，中央处理单元和至少一个外围设备。 中央处理单元通过将所选择的软件应用程序从非易失性存储器传送到易失性存储器并且从易失性存储器执行与所选择的软件应用程序相关联的指令，由操作系统指导执行多个软件应用程序中的选定的一个。 所述至少一个外围设备包括用于定义多个软件应用的执行上下文的实时时钟。 所述数据处理系统还包括使用模式分析器，其适于存储与所述多个软件应用中的每一个的执行上下文相关联的历史信息，并且使用所述历史信息来指示所述操作系统基于所述历史记录采取至少一个动作 信息。

    THERMAL AWARE DATA PLACEMENT AND COMPUTE DISPATCH IN A MEMORY SYSTEM
    49.
    发明申请
    THERMAL AWARE DATA PLACEMENT AND COMPUTE DISPATCH IN A MEMORY SYSTEM 有权
    热记录数据放置和记忆系统中的计算机分配

    公开(公告)号：US20160086654A1

    公开(公告)日：2016-03-24

    申请号：US14492045

    申请日：2014-09-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan Jayasena ,  Dong Ping Zhang

    IPC: G11C11/4096 ,  G11C5/02 ,  G11C11/4078

    CPC classification number: G11C11/4096 ,  G11C5/025 ,  G11C7/04 ,  G11C8/12

    Abstract: A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.

    Abstract translation: 管理存储器系统中的热水平的方法可以包括确定与存储器结构中的多个位置中的每一个相关联的预期热水平，以及针对存储器结构的多个操作的每个操作，将操作分配给 基于与操作相关联的热惩罚和与目标位置相关联的预期热水平，存储器结构中的多个物理位置的目标位置。

    POWER AND PERFORMANCE MANAGEMENT OF ASYNCHRONOUS TIMING DOMAINS IN A PROCESSING DEVICE
    50.
    发明申请
    POWER AND PERFORMANCE MANAGEMENT OF ASYNCHRONOUS TIMING DOMAINS IN A PROCESSING DEVICE 审中-公开
    异步时序域在处理设备中的功率和性能管理

    公开(公告)号：US20160077545A1

    公开(公告)日：2016-03-17

    申请号：US14489130

    申请日：2014-09-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Wayne P. Burleson ,  Manish Arora ,  Indrani Paul ,  Yasuko Eckert

    IPC: G06F1/08 ,  G06F1/26

    CPC classification number: G06F1/12 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: A processing device includes a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain. A queue is used to convey data between the producing processor unit and the consuming processor unit. A system management unit is to modify one or both of an operating frequency or an operating voltage of one or both of the producing processor unit or the consuming processor unit based on a rate of change of a fullness of the queue.

    Abstract translation: 处理装置包括在第一定时域中的产生处理器单元和与第一定时域异步的第二定时域中的消耗处理器单元。 队列用于在生成处理器单元和消费处理器单元之间传送数据。 系统管理单元基于队列的丰满度的变化率来修改生成处理器单元或消费处理器单元中的一个或两个的操作频率或工作电压中的一个或两个。

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