公开(公告)号：US07979151B2

公开(公告)日：2011-07-12

申请号：US11951503

申请日：2007-12-06

申请人： Vincent J. McGahay

发明人： Vincent J. McGahay

IPC分类号： G06F19/00

CPC分类号： G06Q10/06

摘要： Disclosed herein are embodiments of an automated manufacturing system that is used to process multiple jobs in a product fabrication environment, where such processing comprises performing the same multiple consecutive process steps for each job and where each process step can be accomplished using one or more different available processing tools. The manufacturing system incorporates a unique run-time dispatch system. This dispatch system schedules the order in which jobs will be processed and further randomly assigns a particular combination of process steps and tools to each job in such a way that the processing tools are evenly distributed across the jobs. Ensuring even distribution of processing tools allows a statistical process control system to not only detect, for a given process step, product variability outside desired specifications, but also to efficiently de-convolve such product variability.

摘要翻译： 这里公开的是用于在产品制造环境中处理多个作业的自动化制造系统的实施例，其中这样的处理包括为每个作业执行相同的多个连续的处理步骤，并且其中每个处理步骤可以使用一个或多个不同的可用 加工工具。 制造系统采用独特的运行时调度系统。 该调度系统调度处理作业的顺序，并进一步随机地将每个作业的特定组合处理步骤和工具分配给处理工具均匀地分布在作业中。 确保加工工具的均匀分配允许统计过程控制系统不仅针对给定的工艺步骤检测出期望规格之外的产品变异性，而且还有效地解除这种产品变异性。

公开(公告)号：US07892940B2

公开(公告)日：2011-02-22

申请号：US11851123

申请日：2007-09-06

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越至少一个互连的侧壁。

公开(公告)号：US07473636B2

公开(公告)日：2009-01-06

申请号：US11306825

申请日：2006-01-12

申请人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Vincent J. McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Vincent J. McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

摘要翻译： 在采用双镶嵌互连的集成电路的后端中，互连构件具有第一非保形衬套，其在互连的沟槽级的顶部具有较厚的部分; 以及与第一衬垫结合以阻挡金属填充材料的扩散的共形第二衬垫。

公开(公告)号：US20080185684A1

公开(公告)日：2008-08-07

申请号：US12098479

申请日：2008-04-07

申请人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L29/92

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

公开(公告)号：US06989282B2

公开(公告)日：2006-01-24

申请号：US10815418

申请日：2004-04-01

申请人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L21/66

CPC分类号： G01R31/2881

摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。

公开(公告)号：US06831363B2

公开(公告)日：2004-12-14

申请号：US10319032

申请日：2002-12-12

申请人： Timothy J. Dalton ,  Sanjit K. Das ,  Brett H. Engel ,  Brian W. Herbst ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Kelly Malone ,  Jeffrey R. Marino ,  Arthur Martin ,  Vincent J. McGahay ,  Ian D. Melville ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Timothy J. Dalton ,  Sanjit K. Das ,  Brett H. Engel ,  Brian W. Herbst ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Kelly Malone ,  Jeffrey R. Marino ,  Arthur Martin ,  Vincent J. McGahay ,  Ian D. Melville ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L2348

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

摘要翻译： 用于半导体器件的互连结构包括在较低金属化水平上形成的有机低介电常数（低k）电介质层。 形成的通孔在低k电介质层内，通孔连接在下金属化层形成的下金属化线与上金属化层形成的上金属化线。 通孔被选自具有热膨胀系数（CTE）的材料的结构轴环包围，以便在低k电介质层的热膨胀之后保护通孔不受剪切力的影响。

公开(公告)号：US06821890B2

公开(公告)日：2004-11-23

申请号：US09849530

申请日：2001-05-07

申请人： Vincent J. McGahay ,  Thomas H. Ivers ,  Joyce C. Liu ,  Henry A. Nye, III

发明人： Vincent J. McGahay ,  Thomas H. Ivers ,  Joyce C. Liu ,  Henry A. Nye, III

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.

摘要翻译： 通过提供介入的含锗层，差的粘附层如氮化硅和二氧化硅表现出改善的对铜构件的粘合性。 含锗层是锗锗化锗，氧化锗，氮化锗或其组合。 含锗层增强粘合性，使得不良粘附层不易受到铜构件的分层影响。

公开(公告)号：US06479884B2

公开(公告)日：2002-11-12

申请号：US09893786

申请日：2001-06-29

申请人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

发明人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

IPC分类号： H01L2358

CPC分类号： H01L21/76808 ,  H01L2221/1063

摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

摘要翻译： 抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。 通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多种其它材料 这可能会损坏可流动的氧化物材料。 因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

公开(公告)号：US06331481B1

公开(公告)日：2001-12-18

申请号：US09225477

申请日：1999-01-04

申请人： Anthony K. Stamper ,  Vincent J. McGahay

发明人： Anthony K. Stamper ,  Vincent J. McGahay

IPC分类号： H01L21441

CPC分类号： H01L21/76834 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76819 ,  H01L21/76835 ,  H01L21/76885 ,  H01L2221/1036

摘要： The present invention relates to a method of integrating a low dielectric material such as DLC into a dual or single damascene wiring structure which contains a dielectric material having a dielectric constant of 4.0 or above. This integration is achieved in the present invention by employing a step of etchingback the high dielectric constant material to expose regions of in-laid wiring present in the single or dual damascene structure. Damascene wiring structures, single or dual, prepared using the method of the present invention are also provided herein.

摘要翻译： 本发明涉及一种将诸如DLC的低电介质材料整合到包含介电常数为4.0或更高的介电材料的双或单镶嵌布线结构中的方法。 在本发明中通过采用蚀刻高介电常数材料以暴露存在于单镶嵌结构或双镶嵌结构中的放置布线的区域的步骤来实现该集成。 本文还提供了使用本发明的方法制备的单层或双层的镶嵌线路结构。

公开(公告)号：US06329280B1

公开(公告)日：2001-12-11

申请号：US09311470

申请日：1999-05-13

申请人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

发明人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L2221/1063

摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.