公开(公告)号：US20060223216A1

公开(公告)日：2006-10-05

申请号：US11208269

申请日：2005-08-18

申请人： Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Yi Chang ,  Cheng-Hsu Hsiao

发明人： Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Yi Chang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/00 ,  H01L23/495

CPC分类号： H01L27/14618 ,  H01L24/97 ,  H01L25/167 ,  H01L27/14625 ,  H01L27/14683 ,  H01L2224/32225 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A sensor module structure and a method for fabricating the same are proposed. A chip carrier module plate including a plurality of chip carriers is provided, each chip carrier having a first surface and a second surface. At least one semiconductor chip is mounted on and electrically connected to the first surface of each of the chip carriers. An encapsulation body is formed for completely encapsulating the semiconductor chips and the first surfaces of the chip carriers. A singulation process is performed to form individual package units integrated with the semiconductor chips. A sensor chip, a corresponding lens kit and a flexible printed circuit (FPC) board are attached to the second surface of each of the chip carriers, wherein the sensor chip and the FPC board are electrically connected to the chip carrier. This provides the sensor module structure fabricated with simple processes, low costs and high yields.

摘要翻译： 提出了一种传感器模块结构及其制造方法。 提供了包括多个芯片载体的芯片载体模块板，每个芯片载体具有第一表面和第二表面。 至少一个半导体芯片安装在每个芯片载体的第一表面上并电连接到每个芯片载体的第一表面。 形成用于完全封装半导体芯片和芯片载体的第一表面的封装体。 执行单个处理以形成与半导体芯片集成的单个封装单元。 传感器芯片，相应的透镜套件和柔性印刷电路板（FPC）板安装在每个芯片载体的第二表面上，其中传感器芯片和FPC基板电连接到芯片载体。 这提供了以简单的工艺制造的传感器模块结构，低成本和高产量。

公开(公告)号：US20060145362A1

公开(公告)日：2006-07-06

申请号：US11207472

申请日：2005-08-18

申请人： Chin-Huang Chang ,  Chih-Ming Huang ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Chin-Huang Chang ,  Chih-Ming Huang ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/28

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package and a fabrication method of the same are proposed. A chip formed with a plurality of electrode pads on an active surface thereof, and a substrate having a first surface, a corresponding second surface and at least one opening penetrating therethrough are provided. A part of the electrode pads of the chip are electrically connected to the second surface of the substrate by bonding wires passing through the opening of the substrate, and the rest of the electrode pads of the chip are electrically connected to the first surface of the substrate by conductive bumps. A molding process is performed to form a first encapsulant on the first surface of the substrate for encapsulating the chip and form a second encapsulant on the second surface of the substrate for encapsulating the bonding wires. A plurality of solder balls are implanted on the second surface of the substrate.

摘要翻译： 提出了一种半导体封装及其制造方法。 提供了在其有效表面上形成有多个电极焊盘的芯片，以及具有第一表面，相应的第二表面和穿过其中的至少一个开口的基板。 芯片的电极焊盘的一部分通过接合通过基板的开口的线电连接到基板的第二表面，并且芯片的其余电极焊盘与基板的第一表面电连接 通过导电凸块。 进行成型工艺以在衬底的第一表面上形成第一密封剂，用于封装芯片，并在衬底的第二表面上形成用于封装接合线的第二密封剂。 在基板的第二表面上注入多个焊球。

公开(公告)号：US20060022315A1

公开(公告)日：2006-02-02

申请号：US10982559

申请日：2004-11-05

申请人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chung-Lun Liu

发明人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chung-Lun Liu

IPC分类号： H01L21/50

CPC分类号： H01L23/49575 ,  H01L23/3135 ,  H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.

摘要翻译： 提出了一种具有堆叠芯片的半导体封装及其制造方法。 半导体封装包括具有多个引线和支撑延伸部的引线框架; 至少一个具有活性表面的预制包装和连接到引线框架的支撑延伸部的非活性表面; 至少一个芯片安装在所述预制包装的有效表面上; 用于将引线框架，预成型封装和芯片电连接的多个接合线; 以及用于封装预制包装，芯片，接合线和引线框架的一部分的密封剂。 预制包装的活性表面用于承载芯片，并且可以用作跳线，以便解决多芯片模块的已知的良好的裸片（KGD）问题。

公开(公告)号：US20050145413A1

公开(公告)日：2005-07-07

申请号：US11043496

申请日：2005-01-25

申请人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Chung-Lun Liu

发明人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Chung-Lun Liu

IPC分类号： H01L23/498 ,  H05K1/02 ,  H05K3/28 ,  H05K1/03 ,  H05K1/00 ,  H05K3/02

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/28 ,  H05K2201/09663 ,  H05K2201/09781 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/4916 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A warpage-preventive circuit board and method for fabricating the same is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

摘要翻译： 提供了一种防翘曲电路板及其制造方法，其中在电绝缘芯层的表面上形成多个导电迹线，并且多个不连续的虚设电路区域设置在电气绝缘电路板的表面上 - 绝缘芯层在没有导电迹线的区域处，其中相邻的虚设电路区域至少间隔开。 在高温制造过程中，虚拟电路区域有助于降低热应力，并且汲取吸收虚拟电路区域的热膨胀，从而防止电路板翘曲和安装在电路板上的芯片的裂纹，使得屈服 并且可以提高制造的半导体器件的可靠性。

公开(公告)号：US20050093143A1

公开(公告)日：2005-05-05

申请号：US10816339

申请日：2004-03-31

申请人： Cheng-Chian Chiang ,  Chih-Ming Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao ,  Min-Nan Tsai

发明人： Cheng-Chian Chiang ,  Chih-Ming Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao ,  Min-Nan Tsai

IPC分类号： G11C5/04 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L23/34 ,  H01L23/28

CPC分类号： H01L23/3121 ,  G11C5/04 ,  H01L23/5388 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package includes two substrates each having a plurality of electrical connection pads, at least one chip mounted on each of the substrates, an encapsulation body formed on each of the substrates for encapsulating the chip, and an cover for receiving the substrates and the chips therein. The chip is electrically connected to the electrical connection pads. The electrical connection pads are exposed from the cover and located on the same surface or oppositely arranged. The substrates and the cover each substantially has a rectangular shape, with a longer side of each of the substrates being vertical to a longer side of the cover. The semiconductor package is incorporated with multiple chips to enhance the performance and memory capacity thereof, and the substrates are smaller than those in the prior art and thus are more cost-effective to fabricate.

公开(公告)号：US20050006785A1

公开(公告)日：2005-01-13

申请号：US10913977

申请日：2004-08-05

申请人： Chung-Lun Liu ,  Chin-Huang Chang

发明人： Chung-Lun Liu ,  Chin-Huang Chang

IPC分类号： H01L25/065 ,  H01L35/24

CPC分类号： H01L23/02 ,  H01L24/29 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29324 ,  H01L2224/29347 ,  H01L2224/29386 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83138 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01007 ,  H01L2924/01074 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/05032 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： A manufacturing method for a multi-chip module is provided, which is designed to pack two or more semi-conductor chips in a stacked manner over a chip carrier in a single package. An adhesive with fillers allows a second chip to be superimposed over a first chip after the first chip is electrically connected to the chip carrier. The diameter of the fillers is higher than loop height of the bonding wires that are positioned above the active surface of the first chip to prevent the bonding wires to come in contact with the second chip. Moreover, the other embodiment of the fillers (such as copper or aluminum) with high thermal conductivity is also capable of enhancing heat dissipation of the stacked package application.

摘要翻译： 提供了一种用于多芯片模块的制造方法，其被设计成在单个封装中以堆叠的方式在芯片载体上包装两个或更多个半导体芯片。 具有填料的粘合剂允许在第一芯片电连接到芯片载体之后将第二芯片叠加在第一芯片上。 填料的直径高于位于第一芯片的有效表面上方的接合线的环路高度，以防止接合线与第二芯片接触。 此外，具有高导热性的填料（例如铜或铝）的另一个实施方案也能够增强层叠包装应用的散热。

公开(公告)号：USD498760S1

公开(公告)日：2004-11-23

申请号：US29196558

申请日：2003-12-30

申请人： Cheng-Chia Chiang ,  Chih-Ming Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao ,  Min-Nan Tsai

设计人： Cheng-Chia Chiang ,  Chih-Ming Huang ,  Chin-Huang Chang ,  Cheng-Hsu Hsiao ,  Min-Nan Tsai

公开(公告)号：US06737737B1

公开(公告)日：2004-05-18

申请号：US10355610

申请日：2003-01-31

申请人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Jung-Pin Huang

发明人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Jung-Pin Huang

IPC分类号： H01L23495

CPC分类号： H01L23/16 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package with a chip supporting member is provided, including a lead frame having a die pad and a plurality of leads, and a chip supporting member mounted on a central portion of the die pad. The chip supporting member has a first surface and an opposing second surface attached to the die pad. At least a chip is mounted on the first surface of the chip supporting member to space the chip apart from the die pad via the chip supporting member, so as to prevent the chip from being damaged by thermal stress induced by CTE (coefficient of thermal expansion) mismatch between the chip and lead frame, thereby eliminating delamination, warpage and chip cracks. Moreover, the chip supporting member interposed between the chip and die pad provides greater flexibility for mounting variously sized or shaped chips on the die pad without having to use chips corresponding to profile of the die pad.

摘要翻译： 提供一种具有芯片支撑构件的半导体封装，包括具有管芯焊盘和多个引线的引线框架，以及安装在管芯焊盘的中心部分的芯片支撑构件。 芯片支撑构件具有附接到管芯焊盘的第一表面和相对的第二表面。 至少芯片安装在芯片支撑部件的第一表面上，以通过芯片支撑部件将芯片与芯片焊盘隔开，以防止芯片被CTE引起的热应力（热膨胀系数 ）芯片和引线框架之间的不匹配，从而消除分层，翘曲和芯片裂纹。 此外，插入在芯片和芯片焊盘之间的芯片支撑构件提供了更大的灵活性，用于在芯片焊盘上安装各种尺寸或形状的芯片，而不必使用对应于芯片焊盘轮廓的芯片。