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48 条记录 (耗时 0.026 秒)

    Printed circuit board and method for fabricating the same
    5.
    发明授权
    Printed circuit board and method for fabricating the same 有权
    印刷电路板及其制造方法

    公开(公告)号：US07205485B2

    公开(公告)日：2007-04-17

    申请号：US10831247

    申请日：2004-04-23

    申请人： Chin-Tien Chiu ,  Chin-Huang Chang ,  Chih-Ming Huang

    发明人： Chin-Tien Chiu ,  Chin-Huang Chang ,  Chih-Ming Huang

    IPC分类号： H05K1/16

    CPC分类号： H05K3/305 ,  H05K3/28 ,  H05K3/284 ,  H05K2201/0187 ,  H05K2201/09072 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49146

    摘要： A printed circuit board and a method for fabricating the same is provided. A substrate having a core layer and a plurality of pairs of bond pads thereon is prepared with at least one opening formed on the core layer between each pair of the bond pads. A solder mask layer covers the core layer and fills the openings, with recessed portions formed at positions of the solder mask layer on the openings during curing of the solder mask layer. When a small passive component is mounted on the printed circuit board, a space is formed between the bottom of the passive component and the recessed portions of the solder mask layer. An encapsulating resin can flow into the space to form an insulating barrier between the bond pads to prevent bridging between the bond pads and short circuiting of the passive component.

    摘要翻译： 提供一种印刷电路板及其制造方法。 制备具有芯层和其上的多对接合焊盘的衬底，其中在每对接合焊盘之间的芯层上形成有至少一个开口。 焊接掩模层覆盖芯层并填充开口，其中凹陷部分形成在焊料掩模层固化期间在开口上的焊料掩模层的位置处。 当将小的无源部件安装在印刷电路板上时，在无源部件的底部和焊料掩模层的凹部之间形成空间。 封装树脂可以流入空间，以在接合焊盘之间形成绝缘屏障，以防止接合焊盘之间的桥接和无源部件的短路。

    Semiconductor package with chip supporting member
    6.
    发明授权
    Semiconductor package with chip supporting member 失效
    半导体封装带芯片支撑件

    公开(公告)号：US06737737B1

    公开(公告)日：2004-05-18

    申请号：US10355610

    申请日：2003-01-31

    申请人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Jung-Pin Huang

    发明人： Chin-Huang Chang ,  Chin-Tien Chiu ,  Jung-Pin Huang

    IPC分类号： H01L23495

    CPC分类号： H01L23/16 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A semiconductor package with a chip supporting member is provided, including a lead frame having a die pad and a plurality of leads, and a chip supporting member mounted on a central portion of the die pad. The chip supporting member has a first surface and an opposing second surface attached to the die pad. At least a chip is mounted on the first surface of the chip supporting member to space the chip apart from the die pad via the chip supporting member, so as to prevent the chip from being damaged by thermal stress induced by CTE (coefficient of thermal expansion) mismatch between the chip and lead frame, thereby eliminating delamination, warpage and chip cracks. Moreover, the chip supporting member interposed between the chip and die pad provides greater flexibility for mounting variously sized or shaped chips on the die pad without having to use chips corresponding to profile of the die pad.

    摘要翻译： 提供一种具有芯片支撑构件的半导体封装，包括具有管芯焊盘和多个引线的引线框架，以及安装在管芯焊盘的中心部分的芯片支撑构件。 芯片支撑构件具有附接到管芯焊盘的第一表面和相对的第二表面。 至少芯片安装在芯片支撑部件的第一表面上，以通过芯片支撑部件将芯片与芯片焊盘隔开，以防止芯片被CTE引起的热应力（热膨胀系数 ）芯片和引线框架之间的不匹配，从而消除分层，翘曲和芯片裂纹。 此外，插入在芯片和芯片焊盘之间的芯片支撑构件提供了更大的灵活性，用于在芯片焊盘上安装各种尺寸或形状的芯片，而不必使用对应于芯片焊盘轮廓的芯片。

    Fabrication method of multi-chip stack structure
    7.
    发明授权
    Fabrication method of multi-chip stack structure 有权
    多芯片堆叠结构的制作方法

    公开(公告)号：US07981729B2

    公开(公告)日：2011-07-19

    申请号：US12818701

    申请日：2010-06-18

    申请人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    发明人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    IPC分类号： H01L21/60

    CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48496 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

    摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

    摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。