公开(公告)号：US20170125079A1

公开(公告)日：2017-05-04

申请号：US15366083

申请日：2016-12-01

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Chitra K. Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

Abstract: In some examples, a memory device may be configured to use shared read circuitry to sample a voltage drop across both a bit cell and a resistive circuit in order to perform a comparison that produces an output corresponding to the bit stored in the bit cell. The shared read circuitry can include a shared sense amplifier as well as shared N-MOS and P-MOS followers used to apply read voltages across the bit cell and resistive circuit.

公开(公告)号：US20170084324A1

公开(公告)日：2017-03-23

申请号：US15370114

申请日：2016-12-06

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Halbert S. Lin

IPC: G11C11/16 ,  G06F12/0802

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

公开(公告)号：US20170069397A1

公开(公告)日：2017-03-09

申请号：US15356223

申请日：2016-11-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G11C29/50 ,  G11C11/16

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Abstract translation: 在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。 例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配 位单元格。

公开(公告)号：US09542989B2

公开(公告)日：2017-01-10

申请号：US14887426

申请日：2015-10-20

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/16 ,  G11C13/00 ,  G11C5/14

CPC classification number: G11C11/1675 ,  G11C5/147 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C13/0069 ,  G11C2213/79

Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

Abstract translation: 电池偏置控制电路通过自动调节存储器阵列上的读/写路径的多个控制输入，使存储器单元（磁隧道结器件+晶体管）的读/写路径中的器件的性能最大化，而不会超过泄漏电流或可靠性限制 根据电源电压，温度和过程角变化的预定义配置，通过将任何特定参考参数配置文件应用于存储器阵列。

公开(公告)号：US09529672B2

公开(公告)日：2016-12-27

申请号：US14496964

申请日：2014-09-25

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C29/00 ,  G06F11/10

CPC classification number: H03M13/2906 ,  G06F11/1012 ,  G06F11/1076

Abstract: A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction is performed on the data output by each of the input/output pads during a particular period of time.

Abstract translation: 存储器设备包括被配置为存储组织成多个ECC字的数据页的存储器阵列。 存储装置还包括用于与页面相关联的每个ECC字的至少一个输入/输出焊盘，使得存储器装置可以在与页面和第二级相关联的每个ECC字上执行第一级错误校正 在特定时间段内对每个输入/输出焊盘输出的数据执行纠错。

公开(公告)号：US09502089B2

公开(公告)日：2016-11-22

申请号：US14502287

申请日：2014-09-30

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G06F7/02 ,  H03M13/00 ,  G11C11/16 ,  G06F11/08 ,  G11C29/04

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Abstract translation: 在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。 例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配 位单元格。

公开(公告)号：US09443113B2

公开(公告)日：2016-09-13

申请号：US14942665

申请日：2015-11-16

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G06F21/78 ,  G06F21/79 ,  G06F21/86 ,  G11C7/24 ,  G11C11/16 ,  G06F3/06

CPC classification number: G06F21/79 ,  G06F3/062 ,  G06F3/0653 ,  G06F3/0679 ,  G06F21/78 ,  G06F21/86 ,  G06F2221/2143 ,  G11C7/24 ,  G11C11/1695

Abstract: In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.

公开(公告)号：US09418001B2

公开(公告)日：2016-08-16

申请号：US14827628

申请日：2015-08-17

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Dietmar Gogl

IPC: G11C11/00 ,  G06F12/02 ,  G11C7/10 ,  G11C11/4076 ,  G11C8/04 ,  G06F12/06 ,  G11C11/16 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/00

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/7201 ,  G11C7/1042 ,  G11C7/1072 ,  G11C8/04 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/0036

Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.

Abstract translation: 描述了用于交织易失性和非易失性存储器访问的存储器系统和存储器控制器。 在存储器系统中，存储器控制器使用共享地址总线耦合到易失性和非易失性存储器。 激活易失性和非易失性存储器的延迟是不同的，寄存器包含在存储器控制器中用于存储延迟值。 存储器控制器上的附加寄存器存储存储器的预充电延迟以及非易失性存储器的页面大小。 存储器控制器上的存储器访问定序器向存储器发出适当的片选信号以启动其中的操作。

公开(公告)号：US09336848B2

公开(公告)日：2016-05-10

申请号：US14727965

申请日：2015-06-02

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Chitra K. Subramanian

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

Abstract: In some examples, a memory device may be configured to utilize differential bit cells formed from two or more tunnel junctions. In some cases, the tunnel junctions forming the differential bit cell may be arranged to utilize shared read circuitry to reduce device mismatch. For instance, the read operations associated with both tunnel junction may be time multiplexed such that the same preamplifier circuitry may sense voltages representative of the tunnel junctions.

Abstract translation: 在一些示例中，存储器件可以被配置为利用由两个或更多个隧道结形成的差分位单元。 在一些情况下，形成差分位单元的隧道结可以被布置为利用共享读取电路来减少器件失配。 例如，与隧道结相关联的读取操作可以被时间复用，使得相同的前置放大器电路可以感测代表隧道结的电压。

公开(公告)号：US09286218B2

公开(公告)日：2016-03-15

申请号：US14495151

申请日：2014-09-24

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G11C7/12 ,  G11C11/16 ,  G11C7/08 ,  G06F12/08 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/4091 ,  G11C11/56

CPC classification number: G11C11/1675 ,  G06F12/0806 ,  G06F12/0879 ,  G06F2212/62 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/22 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/5607 ,  Y02D10/13

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.

Abstract translation: 在包括本地源线的自旋扭矩磁随机存取存储器（MRAM）中，字线的自动引导用于通过在写入操作期间重新使用已经存在的驱动多个位线的电荷来节省功耗。 通过首先将字线驱动到第一字线电压来实现自动启动。 经过这样的驾驶，字线隔离。 随后驱动电容耦合到字线的多个位线使得字线电压增加到期望的水平，以允许足够的电流流过选定的存储器单元以将信息写入所选存储单元。 另外的实施例包括使用能够进一步升高或保持隔离字线处于所需电压电平的补充电压提供器。