公开(公告)号：US06440752B1

公开(公告)日：2002-08-27

申请号：US09817712

申请日：2001-03-26

申请人： Fengyan Zhang ,  Tingkai Li ,  Hong Ying ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Tingkai Li ,  Hong Ying ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01G706

CPC分类号： H01L28/75 ,  H01L21/31604 ,  H01L21/31683 ,  H01L28/55

摘要： An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.

摘要翻译： 用于铁电体器件的电极包括底部电极; 铁电层; 以及形成在强电介质层上并由金属组合形成的顶部电极，其包括从由铂和铱组成的金属组中的第一金属取得的金属和从由铝和钛组成的金属组中的第二金属; 其中所述顶部电极用作钝化层，并且其中所述顶部电极在氢气氛中的高温退火之后保持导电。 在铁电体器件中形成耐氢电极的方法包括形成底电极; 在底部电极上形成铁电层; 在铁电层上沉积顶部电极; 包括同时从由铂和铱组成的金属组中取出的第一金属; 和从由铝和钛组成的金属组中获取的第二金属; 以及通过在氧气氛中对所述结构退火以在所述顶部电极上形成氧化物钝化层来形成钝化层。

公开(公告)号：US06410343B1

公开(公告)日：2002-06-25

申请号：US09301420

申请日：1999-04-28

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/31691 ,  C23C16/40 ,  H01L21/31604 ,  Y10S438/933 ,  Y10T428/12674 ,  Y10T428/12701 ,  Y10T428/12875

摘要： A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

摘要翻译： 铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均粒径为约0.5微米，晶粒尺寸均匀度的偏差小于10％。 对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。 这些胶片还显示出无疲劳特性：在1x109个开关周期内没有观察到疲劳。 泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。 介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。

公开(公告)号：US06350699B1

公开(公告)日：2002-02-26

申请号：US09584407

申请日：2000-05-30

申请人： Jer-shen Maa ,  Fengyan Zhang

发明人： Jer-shen Maa ,  Fengyan Zhang

IPC分类号： H01L2100

CPC分类号： H01L21/32136 ,  C23F4/00

摘要： A method of anisotropically etching metals, especially iridium, platinum, ruthenium, osmium, and rhenium using a non-chlorofluorocarbon, fluorine-based chemistry. A substrate having metal deposited thereon, is inserted into an ECR plasma etch chamber and heated. A fluorine containing gas, such as, carbon tetrafluoride (CF4), nitrogen trifluoride (NF3) or sulfur hexafluoride (SF6) is introduced into the chamber and ionized to form a plasma. Fluorine ions within the plasma strike, or contact, the metal to form volatile metal-fluorine compounds. The metal-fluorine compounds are exhausted away from the substrate to reduce, or eliminate, redeposition of etch reactants.

摘要翻译： 使用非氯氟烃氟基化学物质各向异性蚀刻金属，特别是铱，铂，钌，锇和铼的方法。 将其上沉积有金属的衬底插入到ECR等离子体蚀刻室中并加热。 将四氟化碳（CF 4），三氟化氮（NF 3）或六氟化硫（SF 6）等含氟气体引入室内并离子化形成等离子体。 等离子体内的氟离子冲击，或接触金属，形成挥发性金属氟化合物。 金属 - 氟化合物从衬底排出，以减少或消除蚀刻反应物的再沉积。

公开(公告)号：US09371226B2

公开(公告)日：2016-06-21

申请号：US13019879

申请日：2011-02-02

申请人： Robert V. Fox ,  Fengyan Zhang ,  Rene G. Rodriguez ,  Joshua J. Pak ,  Chivin Sun

发明人： Robert V. Fox ,  Fengyan Zhang ,  Rene G. Rodriguez ,  Joshua J. Pak ,  Chivin Sun

IPC分类号： H01L31/02 ,  H01L31/18 ,  C01B17/00 ,  B82Y30/00 ,  C01G15/00 ,  H01L31/032 ,  H01L31/0392 ,  H01L31/0749

CPC分类号： B82Y30/00 ,  C01G15/006 ,  C01P2002/72 ,  C01P2002/84 ,  C01P2004/62 ,  C01P2004/64 ,  C01P2006/40 ,  H01L31/0322 ,  H01L31/03923 ,  H01L31/0749 ,  Y02E10/541

摘要： Single source precursors or pre-copolymers of single source precursors are subjected to microwave radiation to form particles of a I-III-VI2 material. Such particles may be formed in a wurtzite phase and may be converted to a chalcopyrite phase by, for example, exposure to heat. The particles in the wurtzite phase may have a substantially hexagonal shape that enables stacking into ordered layers. The particles in the wurtzite phase may be mixed with particles in the chalcopyrite phase (i.e., chalcopyrite nanoparticles) that may fill voids within the ordered layers of the particles in the wurtzite phase thus produce films with good coverage. In some embodiments, the methods are used to form layers of semiconductor materials comprising a I-III-VI2 material. Devices such as, for example, thin-film solar cells may be fabricated using such methods.

摘要翻译： 将单源前体或单源前体的预共聚物进行微波辐射以形成I-III-VI2材料的颗粒。 这样的颗粒可以以纤锌矿相形成，并且可以通过例如暴露于热而转变成黄铜矿相。 纤锌矿相中的颗粒可以具有基本上六边形的形状，其能够堆叠成有序层。 纤锌矿相中的颗粒可以与黄铜矿相中的颗粒（即，黄铜矿纳米颗粒）混合，其可以填充纤锌矿相中颗粒的有序层内的空隙，从而产生具有良好覆盖率的膜。 在一些实施例中，所述方法用于形成包含I-III-VI2材料的半导体材料层。 可以使用这样的方法来制造诸如薄膜太阳能电池的装置。

公开(公告)号：US07905013B2

公开(公告)日：2011-03-15

申请号：US11809959

申请日：2007-06-04

申请人： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

IPC分类号： H01K3/10

CPC分类号： A61N1/0543 ,  B82Y15/00 ,  B82Y30/00 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T428/24998

摘要： An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.

摘要翻译： 提供氧化铱（IrOx）纳米线神经传感器阵列及相关制造方法。 该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。 基板可以是诸如Si，SiO 2，石英，玻璃或聚酰亚胺的材料，并且导电层是诸如ITO，SnO 2，ZnO，TiO 2，掺杂的ITO，掺杂的SnO 2，掺杂的ZnO，掺杂的TiO 2，TiN， TaN，Au，Pt或Ir。 电介质层被选择性地湿蚀刻，与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面，并且可以被成形为圆形，矩形或椭圆形。

公开(公告)号：US20090024182A1

公开(公告)日：2009-01-22

申请号：US12240501

申请日：2008-09-29

申请人： Fengyan Zhang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： A61N1/36

CPC分类号： C30B25/00 ,  A61N1/0543 ,  B82Y5/00 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/16 ,  C30B29/605 ,  Y10S977/811 ,  Y10S977/904 ,  Y10S977/932

摘要： An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x≦4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.

摘要翻译： 提供了具有氧化铱（IrOx）电极神经接口的光学器件及相应的制造方法。 该方法提供了一个衬底并且形成了覆盖衬底的第一导电电极。 具有第一电接口的光电器件连接到第一电极。 光电器件的第二电接口连接到形成在光伏器件上的第二导电电极。 形成了覆盖第二电极的神经界面单晶IrOx纳米结构阵列，其中x <= 4。 IrOx纳米结构可以部分地涂覆有电绝缘体，例如SiO 2，SiN，TiO 2或旋转玻璃（SOG），留下IrOx远端暴露。 在一个方面，为了定向IrOx纳米结构的生长方向，形成了由诸如LiNbO 3，LiTaO 3或SA的材料制成的第二电极表面上的缓冲层。

公开(公告)号：US07446014B2

公开(公告)日：2008-11-04

申请号：US11580623

申请日：2006-10-12

申请人： Fengyan Zhang ,  David R. Evans ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/20

CPC分类号： H01G9/07 ,  Y10S977/762 ,  Y10T29/417

摘要： A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface. A top electrode is formed overlying the nanowire shells. A main cavity is formed between the top electrode and bottom electrodes, partially displaced by a first plurality of nanowire shells. Electrolyte cavities are formed between the sleeves and nanowires by etching the first sacrificial layer. In one aspect, electrolyte cavities are formed between the bottom electrode top surface and a shell coating layer joining the sleeve bottom openings. Then, the main and electrolyte cavities are filled with either a liquid or gas phase electrolyte. In a different aspect, the first sacrificial layer is a solid phase electrolyte that is not etched away.

公开(公告)号：US07256429B2

公开(公告)日：2007-08-14

申请号：US11314222

申请日：2005-12-21

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

IPC分类号： H01L21/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

摘要翻译： 提供了一种用于形成缓冲层存储单元的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。 在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。 顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域 和0.6，厚度在10至200nm的范围内。

公开(公告)号：US07255745B2

公开(公告)日：2007-08-14

申请号：US10971330

申请日：2004-10-21

申请人： Fengyan Zhang ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

IPC分类号： C30B29/62

CPC分类号： H01L24/48 ,  C30B25/005 ,  C30B29/16 ,  C30B29/62 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/43827 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45178 ,  H01L2224/45181 ,  H01L2224/45565 ,  H01L2224/45599 ,  H01L2224/45688 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48599 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/14 ,  H01L2924/20751 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/811 ,  H01L2924/00014 ,  H01L2924/20651 ,  H01L2924/00 ,  H01L2924/01006

摘要： Iridium oxide (IrOx) nanowires and a method forming the nanowires are provided. The method comprises: providing a growth promotion film with non-continuous surfaces, having a thickness in the range of 0.5 to 5 nanometers (nm), and made from a material such as Ti, Co, Ni, Au, Ta, polycrystalline silicon (poly-Si), SiGe, Pt, Ir, TiN, or TaN; establishing a substrate temperature in the range of 200 to 600 degrees C.; introducing oxygen as a precursor reaction gas; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx nanowires from the growth promotion film surfaces. The IrOx nanowires have a diameter in the range of 100 to 1000 Å, a length in the range of 1000 Å to 2 microns, an aspect ratio (length to width) of greater than 50:1. Further, the nanowires include single-crystal nanowire cores covered with an amorphous layer having a thickness of less than 10 Å.

摘要翻译： 提供氧化铱（IrOx）纳米线和形成纳米线的方法。 该方法包括：提供具有0.5至5纳米（nm）范围内的厚度的非连续表面的生长促进膜，并由诸如Ti，Co，Ni，Au，Ta，多晶硅 多晶硅），SiGe，Pt，Ir，TiN或TaN; 建立200〜600℃的基板温度。 引入氧气作为前体反应气体; 引入（甲基环戊二烯基）（1,5-环辛二烯）铱（I）前体; 使用金属有机化学气相沉积（MOCVD）工艺，从生长促进膜表面生长IrOx纳米线。 IrOx纳米线的直径在100至1000埃的范围内，长度在1000埃至2微米之间，纵横比（长宽比）大于50:1。 此外，纳米线包括覆盖有厚度小于Å的非晶层的单晶纳米线芯。

公开(公告)号：US07169637B2

公开(公告)日：2007-01-30

申请号：US10883228

申请日：2004-07-01

申请人： Fengyan Zhang ,  Lisa H. Stecker ,  Bruce D. Ulrich ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Lisa H. Stecker ,  Bruce D. Ulrich ,  Sheng Teng Hsu

IPC分类号： H01L21/06 ,  H01L21/461

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.

摘要翻译： 包含含PCMO的RRAM以减少堆叠侧壁残留物的单掩模蚀刻方法包括制备从由硅，二氧化硅和多晶硅组成的一组衬底取得的衬底; 在底物上沉积底部电极; 在底部电极上沉​​积PCMO层; 在PCMO层上沉积顶部电极; 在顶部电极上沉​​积硬掩模; 在硬掩模上沉积和图案化光致抗蚀剂层; 蚀刻硬掩模; 使用具有由Ar，O 2和Cl 2组成的蚀刻气氛的第一蚀刻工艺蚀刻顶部电极; 使用从由第一蚀刻工艺和由Ar和O 2组成的蚀刻气氛的第二蚀刻工艺组成的蚀刻工艺组中的蚀刻工艺来蚀刻PCMO层。 使用第一蚀刻工艺蚀刻底部电极; 并完成RRAM设备。