公开(公告)号：US10163633B2

公开(公告)日：2018-12-25

申请号：US15457200

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao Beng Law ,  Xunyuan Zhang ,  Errol Todd Ryan ,  Nicholas LiCausi

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/3065 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027

Abstract: Methods of forming non-mandrel cuts. A dielectric layer is formed on a metal hardmask layer, and a patterned sacrificial layer is formed on the dielectric layer. The dielectric layer is etched to form a non-mandrel cut in the dielectric layer that is vertically aligned with the opening in the patterned sacrificial layer. A metal layer is formed on an area of the metal hardmask layer exposed by the non-mandrel cut in the dielectric layer. The metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.

公开(公告)号：US09583380B2

公开(公告)日：2017-02-28

申请号：US14334385

申请日：2014-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol Todd Ryan

IPC: H01L21/76 ,  H01L21/4763 ,  H01L23/532 ,  H01L29/06 ,  H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/76802 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one example, a method includes forming a mask layer above or in a dielectric material. The dielectric material is exposed to photon radiation in an ambient atmosphere comprising a carbon gettering agent to generate damaged portions of the dielectric material. The mask layer blocks the photon radiation. The damaged portions of the dielectric material are removed.

Abstract translation: 在一个实例中，一种方法包括在电介质材料上方或介质材料中形成掩模层。 电介质材料在包含碳吸气剂的环境气氛中暴露于光子辐射，以产生电介质材料的损坏部分。 掩模层阻挡光子辐射。 去除电介质材料的损坏部分。

公开(公告)号：US09559059B2

公开(公告)日：2017-01-31

申请号：US14526678

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Errol Todd Ryan

IPC: H01L21/44 ,  H01L23/535 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成开口，从而暴露至少一部分导电接触，执行选择性沉积工艺以在开口中选择性地形成导电材料层 并且在导电接触上，执行退火工艺，在选择性地形成的导电材料层上方沉积至少一种导电材料，以便过度填充该开口，以及执行至少一个平坦化工艺以便去除多余的材料， 导电通孔，其定位在开口中并且导电地耦合到导电接触。

公开(公告)号：US09530691B1

公开(公告)日：2016-12-27

申请号：US15048280

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Errol Todd Ryan

IPC: H01L21/8242 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/288 ,  H01L21/66 ,  H01L21/67

CPC classification number: H01L21/76897 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/288 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/67075 ,  H01L21/67098 ,  H01L21/67253 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/20

Abstract: At least one method, apparatus and system disclosed herein for forming an integrated circuit having a dual-orientation self aligned via. A first dielectric layer is formed on a semiconductor substrate. At least one first metal feature is formed in a first metal layer. A first cap feature is deposited over the first metal feature. A manganese silicate etch stop layer is formed above the dielectric layer. An etch process is performed for removing for at least removing the first cap feature. A second metal feature is formed in a second metal layer. A dual-orientation self aligned via connecting a portion of the second metal feature to the first metal feature is formed.

Abstract translation: 本文公开的用于形成具有双向自对准通孔的集成电路的至少一种方法，装置和系统。 第一电介质层形成在半导体衬底上。 在第一金属层中形成至少一个第一金属特征。 第一盖特征被放置在第一金属特征上。 在电介质层上方形成硅酸铝蚀刻停止层。 执行蚀刻处理以移除以至少去除第一盖特征。 在第二金属层中形成第二金属特征。 形成通过将第二金属特征的一部分连接到第一金属特征的双向自对准。

公开(公告)号：US08932934B2

公开(公告)日：2015-01-13

申请号：US13903283

申请日：2013-05-28

Applicant: GlobalFoundries Inc.

Inventor： Moosung M. Chae ,  Errol Todd Ryan ,  Nicholas Vincent Licausi ,  Christian Witt ,  Ailian Zhao ,  Ming He ,  Sean X. Lin ,  Xunyuan Zhang ,  Kunaljeet Tanwar

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/48 ,  H01L21/316 ,  H01L21/02

CPC classification number: H01L21/76831 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76843 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.

Abstract translation: 提供了一种用于在半导体制造期间减少超低k层的自形成势垒的污染的方法的方法。 一方面，一种方法包括：提供包含至少一个沟槽的固化的超低k膜，并且用孔填充材料填充膜的孔; 在沟槽的表面去除暴露的孔隙填充材料以形成暴露的孔; 并在沟槽的表面上形成自形成阻挡层。

公开(公告)号：US20140227872A1

公开(公告)日：2014-08-14

申请号：US13766898

申请日：2013-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L2221/1063

Abstract: One illustrative method disclosed herein includes performing a first etching process to define a via opening in a layer of insulating material, performing at least one process operation to form a sacrificial liner layer on the sidewalls of the via opening, performing a second etching process to define a trench in the layer of insulating material, wherein the sacrificial liner layer is exposed to the second etching process, after performing the second etching process, performing a third etching process to remove the sacrificial liner layer and, after performing the third etching process, forming a conductive structure in at least the via opening and the trench.

Abstract translation: 本文公开的一种说明性方法包括执行第一蚀刻工艺以在绝缘材料层中限定通孔开口，执行至少一个工艺操作以在通孔开口的侧壁上形成牺牲衬垫层，执行第二蚀刻工艺以界定 在所述绝缘材料层中的沟槽，其中所述牺牲衬垫层在进行所述第二蚀刻工艺之后暴露于所述第二蚀刻工艺，执行第三蚀刻工艺以去除所述牺牲衬垫层，并且在执行所述第三蚀刻工艺之后，形成 至少在通孔开口和沟槽中的导电结构。

公开(公告)号：US20180130699A1

公开(公告)日：2018-05-10

申请号：US15345882

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76813 ,  H01L21/76808 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53257

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

公开(公告)号：US09831174B1

公开(公告)日：2017-11-28

申请号：US15168899

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/5226 ,  H01L21/02244 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76864 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53252 ,  H01L23/53295

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US09613906B2

公开(公告)日：2017-04-04

申请号：US14311457

申请日：2014-06-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Errol Todd Ryan ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76853 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76868 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes contacting a liner that is disposed adjacent to a porous interlayer dielectric (ILD) layer of dielectric material with a selectively reactive gas at reaction conditions. A portion of the liner is reacted with the selectively reactive gas to form a converted expanded portion that is disposed between a remaining portion of the liner and the porous ILD layer.

公开(公告)号：US09520321B2

公开(公告)日：2016-12-13

申请号：US14633914

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Errol Todd Ryan ,  Sean X. Lin

IPC: H01L21/44 ,  H01L29/40 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76805 ,  H01L21/76829 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit includes forming a first conductive interconnect line overlying a semiconductor substrate. The method forms an insulator cap defining a gap overlying the first conductive interconnect line. An upper interlayer dielectric material is deposited over the insulator cap and in the gap over the first conductive interconnect line. A via is etched through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line. The method deposits a conductive material into the via to form a conductive via in contact with the first conductive interconnect line.

Abstract translation: 公开了用于制造具有自对准通孔的集成电路的集成电路和方法。 一种用于制造集成电路的方法包括形成覆盖半导体衬底的第一导电互连线。 该方法形成限定覆盖在第一导电互连线上的间隙的绝缘体帽。 在绝缘体盖上并在第一导电互连线上的间隙中沉积上层间绝缘材料。 将通孔蚀刻通过上层间介电材料并进入间隙以露出第一导电互连线。 该方法将导电材料沉积到通孔中以形成与第一导电互连线接触的导电通孔。