公开(公告)号：US20180269295A1

公开(公告)日：2018-09-20

申请号：US15458482

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Alvin J. Joseph ,  John J. Ellis-Monaghan

IPC: H01L29/423 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/06 ,  H01L21/265 ,  H01L29/08 ,  H01L29/78 ,  H01L21/768 ,  H01L23/48 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/42376 ,  H01L21/26513 ,  H01L21/28097 ,  H01L21/28114 ,  H01L21/28167 ,  H01L21/31111 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/4991 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78609

Abstract: Device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor. A first dielectric layer is formed, and a second dielectric layer are formed on the first dielectric layer. An opening is formed that extends vertically through the first and second dielectric layers. After the first opening is formed, the second dielectric layer is laterally recessed relative to the first dielectric layer with a selective etching process, which widens a portion of the opening extending vertically through the second dielectric layer relative to a portion of the opening extending vertically through the first dielectric layer. After the second dielectric layer is laterally recessed, a gate electrode is formed that includes a narrow section in the portion of the opening extending vertically through the first dielectric layer and a wide section in the portion of the opening extending vertically through the second dielectric layer.

公开(公告)号：US20180233401A1

公开(公告)日：2018-08-16

申请号：US15951557

申请日：2018-04-12

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Steven M. Shank ,  Michel Abou-Khalil

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76286 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.

公开(公告)号：US20180166536A1

公开(公告)日：2018-06-14

申请号：US15372929

申请日：2016-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan

IPC: H01L29/10 ,  H01L23/66 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/762 ,  H01L21/76283 ,  H01L21/764 ,  H01L21/823481 ,  H01L23/66 ,  H01L25/18 ,  H01L29/0649 ,  H01L29/78 ,  H01L2223/6683

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to active and passive radio frequency (RF) components with deep trench isolation structures and methods of manufacture. The structure includes a bulk high resistivity wafer with a deep trench isolation structure having a depth deeper than a maximum depletion depth at worst case voltage bias difference between devices which are formed on the bulk high resistivity wafer.

公开(公告)号：US09954137B2

公开(公告)日：2018-04-24

申请号：US15594951

申请日：2017-05-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  John C. S. Hall ,  Marwan H. Khater ,  Edward W. Kiewra ,  Steven M. Shank

IPC: H01L21/00 ,  H01L31/20 ,  H01L27/146 ,  H01L31/028 ,  H01L31/0203 ,  H01L21/02

CPC classification number: H01L31/202 ,  H01L21/02667 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/14692 ,  H01L27/14694 ,  H01L27/14698 ,  H01L31/0203 ,  H01L31/028 ,  H01L31/208

Abstract: Photodetector structures and methods of manufacture are provided. The method includes forming undercuts about detector material formed on a substrate. The method further includes encapsulating the detector to form airgaps from the undercuts. The method further includes annealing the detector material causing expansion of the detector material into the airgaps.

公开(公告)号：US09882081B2

公开(公告)日：2018-01-30

申请号：US15227081

申请日：2016-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  John C. S. Hall ,  Marwan H. Khater ,  Edward W. Kiewra ,  Steven M. Shank

IPC: H01L27/144 ,  H01L31/0203 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/105 ,  H01L31/18 ,  H01L31/103 ,  H01L27/146 ,  H01L31/0232

CPC classification number: H01L31/1808 ,  H01L27/1443 ,  H01L27/1446 ,  H01L27/14629 ,  H01L31/0203 ,  H01L31/02161 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/103 ,  H01L31/105 ,  H01L31/1872

Abstract: Disclosed are a method of forming a photodetector and a photodetector structure. In the method, a polycrystalline or amorphous light-absorbing layer is formed on a dielectric layer such that it is in contact with a monocrystalline semiconductor core of an optical waveguide. The light-absorbing layer is then encapsulated in one or more strain-relief layers and a rapid melting growth (RMG) process is performed to crystallize the light-absorbing layer. The strain-relief layer(s) are tuned for controlled strain relief so that, during the RMG process, the light-absorbing layer remains crack-free. The strain-relief layer(s) are then removed and an encapsulation layer is formed over the light-absorbing layer (e.g., filling in surface pits that developed during the RMG process). Subsequently, dopants are implanted through the encapsulation layer to form diffusion regions for PIN diode(s). Since the encapsulation layer is relatively thin, desired dopant profiles can be achieved within the diffusion regions.

公开(公告)号：US09864132B1

公开(公告)日：2018-01-09

申请号：US15282320

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Roderick A. Augur ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B6/12 ,  H01L23/373 ,  H01L27/092

CPC classification number: G02B6/12 ,  G02B2006/12061 ,  G02B2006/12135 ,  H01L23/373 ,  H01L23/3733 ,  H01L23/3738 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon waveguide devices in integrated photonics and methods of manufacture. The integrated photonics structure includes: a localized region of negative thermal expansion (NTE) coefficient material formed within a trench; at least one photonics or CMOS component contacting with the negative thermal expansion (NTE) coefficient material; and cladding material formed above the at least one photonics or CMOS component.

公开(公告)号：US20170162743A1

公开(公告)日：2017-06-08

申请号：US15441345

申请日：2017-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  John J. Ellis-Monaghan ,  Marwan H. Khater ,  Jason S. Orcutt

IPC: H01L31/18 ,  H01L31/103 ,  H01L31/0352 ,  H01L31/0392 ,  H01L31/0312

CPC classification number: H01L31/1812 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/035272 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1037 ,  H01L31/109 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/50

Abstract: Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

公开(公告)号：US11527432B2

公开(公告)日：2022-12-13

申请号：US17086925

申请日：2020-11-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32 ,  H01L21/02 ,  H01L27/06 ,  H01L29/10

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US10916642B2

公开(公告)日：2021-02-09

申请号：US16388500

申请日：2019-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

公开(公告)号：US10903207B2

公开(公告)日：2021-01-26

申请号：US16258714

申请日：2019-01-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L49/02 ,  H01L29/08 ,  H01L29/45 ,  H01L29/06 ,  H01L27/12 ,  H01L27/105 ,  H01L21/02 ,  H01L21/265 ,  H01L27/088

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.