公开(公告)号：US09123827B2

公开(公告)日：2015-09-01

申请号：US14153502

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann ,  Carsten Grass

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324 ,  H01L21/283 ,  H01L21/02

CPC classification number: H01L21/823835 ,  H01L21/02595 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.

Abstract translation: 一种用于制造集成电路的方法包括：在其上提供包括栅电极结构的半导体衬底和沿着所述栅电极结构的侧壁的侧壁间隔物，沿着所述侧壁形成第一高度，在所述栅电极结构上方形成平坦化碳基聚合物层，以及 并且蚀刻光学平坦化层的一部分以暴露栅电极结构的顶部。 此外，该方法包括蚀刻侧壁间隔物的上部，其选择性地选择栅电极结构，以便露出栅极电极结构的上部的侧壁并在栅电极结构的顶部上沉积硅化物形成材料 以及栅电极结构的上部的侧壁。 此外，该方法包括退火硅化物形成材料。

公开(公告)号：US20150200142A1

公开(公告)日：2015-07-16

申请号：US14153502

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann ,  Carsten Grass

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/283 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/823835 ,  H01L21/02595 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.

Abstract translation: 一种用于制造集成电路的方法包括：在其上提供包括栅电极结构的半导体衬底和沿着所述栅电极结构的侧壁的侧壁间隔物，沿着所述侧壁形成第一高度，在所述栅电极结构上方形成平坦化碳基聚合物层，以及 并且蚀刻光学平坦化层的一部分以暴露栅电极结构的顶部。 此外，该方法包括蚀刻侧壁间隔物的上部，其选择性地选择栅电极结构，以便露出栅极电极结构的上部的侧壁并在栅电极结构的顶部上沉积硅化物形成材料 以及栅电极结构的上部的侧壁。 此外，该方法包括退火硅化物形成材料。

公开(公告)号：US09040405B2

公开(公告)日：2015-05-26

申请号：US14043181

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tom Hasche ,  Sven Beyer ,  Gerhard Lembach ,  Alexander Ebermann

IPC: H01L21/3205 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L21/28123 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823468 ,  Y10S438/942 ,  Y10S438/947

Abstract: A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and on the gate electrode material layer between the mask features, removing the spacer layer from the gate electrode material layer between the mask features, and etching the gate electrode material layer and dielectric material layer using the hard mask features as an etch mask to obtain gate electrode structures. A semiconductor device including first and second gate electrode structures, each covered by a cap layer that comprises a mask material surrounded at the sidewalls thereof by a spacer material different from the mask material, and the distance between the first and second electrode structures is at most 100 nm.

Abstract translation: 一种形成半导体器件的方法，包括在半导体层上形成电介质材料层，在电介质材料层上形成栅电极材料层，在栅电极材料层上形成掩模特征，在栅电极材料层的侧壁上形成间隔层 掩模特征，并且在掩模特征之间的栅电极材料层上，在掩模特征之间从栅电极材料层移除间隔层，并使用硬掩模特征作为蚀刻掩模蚀刻栅电极材料层和电介质材料层， 获得栅电极结构。 一种半导体器件，包括第一和第二栅极电极结构，每个覆盖层包括掩模材料，该掩模材料在其侧壁处被不同于掩模材料的隔离材料包围，并且第一和第二电极结构之间的距离最多为 100nm。

公开(公告)号：US20150137270A1

公开(公告)日：2015-05-21

申请号：US14570292

申请日：2014-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/42364 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: A transistor device includes a gate electrode structure. The gate electrode structure includes a high-k gate insulation layer, a metal-containing first electrode material positioned above the high-k gate insulation layer, and a second electrode material positioned above the metal-containing first electrode material. The high-k gate insulation layer has a length that is less than a length of the second electrode material.

Abstract translation: 晶体管器件包括栅电极结构。 栅电极结构包括高k栅极绝缘层，位于高k栅极绝缘层上方的含金属的第一电极材料和位于含金属的第一电极材料上方的第二电极材料。 高k栅极绝缘层的长度小于第二电极材料的长度。

公开(公告)号：US08786027B2

公开(公告)日：2014-07-22

申请号：US13886373

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L29/76 ,  H01L29/34 ,  H01L31/062 ,  H01L31/119

CPC classification number: H01L29/7827 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/84 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

Abstract translation: 在复杂的半导体器件中，替代栅极方法可以与用于实现应变诱导半导体材料的工艺策略结合使用，其中应变诱导半导体材料的优越接近和/或替代栅极方法的优异鲁棒性可以通过 形成具有优异均匀性的初始栅电极结构，并且在非常先进的制造阶段，即在完成基本晶体管配置之后，提供用于实现应变通道区域的至少一个空腔。

公开(公告)号：US08735270B2

公开(公告)日：2014-05-27

申请号：US13888753

申请日：2013-05-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Klaus Hempel ,  Sven Beyer ,  Markus Lenski ,  Stephan Kruegel

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/28026 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7843

Abstract: In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Abstract translation: 在替代浇口方法中，可以通过在去除占位材料的中间状态下进行材料侵蚀过程来实现闸门开口的优越的横截面形状。 因此，当执行拐角舍入处理顺序时，占位符材料的剩余部分可以有效地保护诸如高k电介质材料的底层敏感材料。

公开(公告)号：US08716136B1

公开(公告)日：2014-05-06

申请号：US13655844

申请日：2012-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Berthold Reimer ,  Johannes von Kluge ,  Sven Beyer

IPC: H01L21/311

CPC classification number: H01L29/6656 ,  H01L21/0206 ,  H01L21/28052 ,  H01L21/31111 ,  H01L29/665 ,  H01L29/7833

Abstract: A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid.

Abstract translation: 本文公开的方法包括提供包括晶体管的半导体结构，所述晶体管包括形成在栅极处的栅电极和氮化硅侧壁间隔物。 执行湿蚀刻工艺。 湿蚀刻工艺去除氮化硅侧壁间隔物的至少一部分。 湿蚀刻工艺包括施加包含氢氟酸和磷酸中的至少一种的蚀刻剂。

公开(公告)号：US20130240988A1

公开(公告)日：2013-09-19

申请号：US13886373

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/84 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

Abstract translation: 在复杂的半导体器件中，替代栅极方法可以与用于实现应变诱导半导体材料的工艺策略结合使用，其中应变诱导半导体材料的优越接近和/或替代栅极方法的优异鲁棒性可以通过 形成具有优异均匀性的初始栅电极结构，并且在非常先进的制造阶段，即在完成基本晶体管配置之后，提供用于实现应变通道区域的至少一个空腔。