公开(公告)号：US20160181285A1

公开(公告)日：2016-06-23

申请号：US15054951

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric C.T. Harley ,  Judson R. Holt ,  Yue Ke ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.

公开(公告)号：US09368492B2

公开(公告)日：2016-06-14

申请号：US14054009

申请日：2013-10-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/82 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02123 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7856

Abstract: A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer; removing the second portion of the SOI layer to expose a portion of the buried insulator layer; forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and forming a semiconductor layer made of a second semiconductor material on the exposed portion of the base semiconductor layer, so that the replacement semiconductor layer covers the exposed region of the buried insulator layer.

Abstract translation: 半导体衬底可以通过提供一种提供绝缘体上半导体（SOI）衬底而形成，该衬底包括基底半导体层，在该半导体基底上方的掩埋绝缘体层，以及包含掩埋绝缘体层之上的第一半导体材料的SOI层 ; 在所述SOI层中形成隔离区，其将所述SOI层的第一部分与所述SOI层的第二部分隔离; 去除所述SOI层的所述第二部分以暴露所述掩埋绝缘体层的一部分; 在所述掩埋绝缘体层的暴露部分中形成孔以暴露所述基底半导体层的一部分; 以及在所述基底半导体层的所述暴露部分上形成由第二半导体材料制成的半导体层，使得所述替换半导体层覆盖所述掩埋绝缘体层的所述暴露区域。

公开(公告)号：US20160163707A1

公开(公告)日：2016-06-09

申请号：US15016612

申请日：2016-02-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Eric C.T. Harley ,  Judson R. Holt ,  Gauri V. Karve ,  Yue Ke ,  Derrick Liu ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa Alyson Smith

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.

Abstract translation: 本发明的实施例提供了一种外延生长FinFET的方法。 一种方法可以包括提供包括绝缘体和底层的半导体衬底; 使用外延生长在所述半导体衬底上形成沟道层; 将凹槽蚀刻到沟道层中并外延地再生沟道层上的一部分; 蚀刻通道层和底层以形成翅片; 形成栅极结构和一组间隔物; 将源漏区蚀刻到沟道层中; 以及在源极漏极区域中形成源极漏极材料。

公开(公告)号：US09362310B2

公开(公告)日：2016-06-07

申请号：US14694243

申请日：2015-04-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/088 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/167 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors.

公开(公告)号：US09331201B2

公开(公告)日：2016-05-03

申请号：US13906428

申请日：2013-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66795

Abstract: A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other.

Abstract translation: 提供半导体结构，其半导体鳍片具有可变的高度，而没有任何不适当的形貌。 半导体结构包括具有第一半导体表面和第二半导体表面的半导体衬底，其中第一半导体表面垂直偏移并位于第二半导体表面上方。 氧化物区域直接位于第一半导体表面和/或第二半导体表面上。 具有第一高度的第一组第一半导体散热片位于半导体衬底的第一半导体表面之上。 具有第二高度的第二组第二半导体翅片位于第二半导体表面上方，其中第二高度不同于第一高度，并且其中每个第一半导体鳍片和每个第二半导体鳍片具有彼此共面的最顶面。

公开(公告)号：US09305883B2

公开(公告)日：2016-04-05

申请号：US14620233

申请日：2015-02-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sebastian Naczas ,  Vamsi Paruchuri ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L23/535 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.

公开(公告)号：US20160086886A1

公开(公告)日：2016-03-24

申请号：US14957842

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L23/525 ,  H01L23/62 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L23/5256 ,  H01L23/5329 ,  H01L23/62 ,  H01L27/0288 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.

公开(公告)号：US09236397B2

公开(公告)日：2016-01-12

申请号：US14172365

申请日：2014-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Jinghong Li ,  Sanjay Mehta ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/16 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L27/1211 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/26506 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A composite spacer structure is formed on vertical sidewalls of a gate structure that is formed straddling a semiconductor fin. In one embodiment, the composite spacer structure includes an inner low-k dielectric material portion and an outer nitride material portion.

Abstract translation: 在跨越半导体鳍片的栅极结构的垂直侧壁上形成复合间隔物结构。 在一个实施例中，复合间隔物结构包括内部低k电介质材料部分和外部氮化物材料部分。

公开(公告)号：US09224811B2

公开(公告)日：2015-12-29

申请号：US14215398

申请日：2014-03-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/15

CPC classification number: H01L29/0673 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/155 ,  H01L29/42392 ,  H01L29/78696

Abstract: A stacked semiconductor device includes a first pair of vertically stacked self-aligned nanowires, a second pair of vertically stacked self-aligned nanowires, and a gate upon a semiconductor substrate, the gate surrounding portions of the first pair of vertically stacked self-aligned nanowires and the second pair of vertically stacked self-aligned nanowires. First epitaxy may merge the first pair of vertically stacked self-aligned nanowires and second epitaxy may merge second pair of vertically stacked self-aligned nanowires. The stacked semiconductor device may be fabricated by forming a lattice-fin upon the semiconductor substrate and the gate surrounding a portion of the lattice-fin. The vertically stacked self-aligned nanowires may be formed by selectively removing a plurality of layers from the lattice-fin.

Abstract translation: 堆叠的半导体器件包括第一对垂直堆叠的自对准纳米线，第二对垂直堆叠的自对准纳米线和半导体衬底上的栅极，第一对垂直堆叠的自对准纳米线的栅极周围部分 和第二对垂直堆叠的自对准纳米线。 第一外延可以合并第一对垂直堆叠的自对准纳米线，并且第二外延可以合并第二对垂直堆叠的自对准纳米线。 层叠的半导体器件可以通过在半导体衬底上形成晶格鳍并围绕晶格鳍的一部分形成栅极来制造。 垂直堆叠的自对准纳米线可以通过从晶格鳍选择性地去除多个层来形成。

公开(公告)号：US20140124840A1

公开(公告)日：2014-05-08

申请号：US13670674

申请日：2012-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。