公开(公告)号：US06275971B1

公开(公告)日：2001-08-14

申请号：US08941898

申请日：1997-09-30

Applicant: Harold J. Levy ,  Subhas Bothra ,  David C. Chapman

Inventor： Harold J. Levy ,  Subhas Bothra ,  David C. Chapman

IPC: G06F1750

CPC classification number: G06F17/5081

Abstract: Disclosed is a method for checking integrated circuit layout design files. The method includes identifying a via geometry that is laid out on a via mask file. Identifying a metallization geometry that is laid out on a metallization mask file. Shifting the via geometry in a first orientation to produce a first shifted via geometry. Performing a logical AND between the first shifted via geometry and the metallization geometry. The method further includes determining whether the logical AND produces a value indicative of a sufficient overlap between the identified metallization geometry and the first shifted via geometry.

Abstract translation: 公开了一种用于检查集成电路布局设计文件的方法。 该方法包括识别布局在通孔掩模文件上的通孔几何。 识别在金属化掩模文件上布置的金属化几何。 在第一方向移动通孔几何以产生第一移位通孔几何形状。 在第一移位通孔几何和金属化几何之间执行逻辑AND。 该方法还包括确定逻辑“否”是否产生指示所识别的金属化几何形状和第一偏移通道几何之间的足够重叠的值。

公开(公告)号：US6159844A

公开(公告)日：2000-12-12

申请号：US87492

申请日：1998-05-29

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/31116

Abstract: Disclosed is a method for fabricating conductive contacts in a dielectric layer that overlies a semiconductor wafer having diffusion regions, shallow trench isolation regions, and gate structures that have a part overlying the shallow trench isolation regions. The method includes forming an oxide layer over the gate structures and forming a photoresist mask over the semiconductor wafer, including the oxide layer over the gate structures. The photoresist mask has windows that define an opening over gate contact locations, and the gate contact locations are defined substantially over the part of the gate structures that overlie the shallow trench isolation regions. The method further includes etching the oxide layer over the gate structures through the windows to define exposed gate structure regions. The method also includes depositing a silicon nitride layer over the semiconductor wafer including the oxide layer over the gate structures and the exposed gate structure regions, and depositing a dielectric layer over the deposited silicon nitride layer. The method then includes etching via holes through the dielectric layer and the silicon nitride layer to define conductive contact vias to both the exposed gate structure regions and diffusion regions.

Abstract translation: 公开了一种在具有扩散区域的半导体晶片，浅沟槽隔离区域和具有覆盖浅沟槽隔离区域的部分的栅极结构的电介质层中制造导电接触的方法。 该方法包括在栅极结构上形成氧化物层，并在半导体晶片上形成光致抗蚀剂掩模，包括栅极结构上的氧化物层。 光致抗蚀剂掩模具有限定在栅极接触位置上的开口的窗口，并且栅极接触位置基本上限定在覆盖在浅沟槽隔离区域上的栅极结构的部分上。 该方法还包括通过窗口蚀刻栅极结构上的氧化物层以限定暴露的栅极结构区域。 该方法还包括在半导体晶片之上沉积包括栅极结构和暴露的栅极结构区域上的氧化物层的氮化硅层，以及在沉积的氮化硅层上沉积介电层。 该方法然后包括通过介电层和氮化硅层蚀刻通孔，以限定暴露的栅极结构区域和扩散区域的导电接触通孔。

公开(公告)号：US6140221A

公开(公告)日：2000-10-31

申请号：US124603

申请日：1998-07-29

Applicant: Rao Venkateswara Annapragada ,  Subhas Bothra

Inventor： Rao Venkateswara Annapragada ,  Subhas Bothra

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/02134 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3121 ,  H01L21/3124 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76831

Abstract: A semiconductor device has a device layer, a conductive structure, such as a conductive line, disposed over the device layer, and a porous dielectric layer disposed over the device layer and the conductive structure. At least one via is formed through the porous dielectric layer to the conductive structure with a second dielectric material formed along sidewalls of the via. Often, the porous dielectric layer includes a hydrophobic aerogel material having silicon-hydrogen bonds. One exemplary method of making the semiconductor device includes forming a conductive structure over a device layer of the semiconductor device and then forming a porous dielectric layer over the device layer and the conductive structure. A first via is formed through the porous dielectric layer to the conductive structure. The first via is filled with a second dielectric material that is less porous than the porous dielectric layer and then a second via is formed through the second dielectric material to the conductive structure.

Abstract translation: 半导体器件具有设置在器件层上的器件层，导电结构，例如导线，以及设置在器件层和导电结构上的多孔介电层。 至少一个通孔通过多孔电介质层形成到导电结构，其中第二电介质材料沿通孔的侧壁形成。 通常，多孔介电层包括具有硅 - 氢键的疏水性气凝胶材料。 制造半导体器件的一个示例性方法包括在半导体器件的器件层上形成导电结构，然后在器件层和导电结构上形成多孔介电层。 通过多孔介电层形成第一通孔到导电结构。 第一通孔填充有比多孔电介质层少孔的第二电介质材料，然后通过第二电介质材料形成导电结构的第二通孔。

公开(公告)号：US6057224A

公开(公告)日：2000-05-02

申请号：US899531

申请日：1997-07-24

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L21/44 ,  H01L21/461

CPC classification number: H01L21/7682 ,  H01L23/4821 ,  H01L23/5221 ,  H01L2924/0002 ,  Y10S438/926

Abstract: A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer and non-sacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer, a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer. Additional similar interconnect structures can be stacked over a base interconnect structure.

Abstract translation: 制造具有空气作为金属化层之间的有效电介质的集成电路互连结构的方法包括以下步骤：a）在衬底上提供牺牲材料的空气电介质形成层; b）在空气电介质形成层中形成柱孔; c）用非牺牲材料填充柱孔; d）在牺牲空气电介质形成层和非牺牲材料柱之上构建金属化层; 以及e）向互连结构施加各向同性蚀刻剂以除去牺牲材料，留下用于金属化层的机械支撑的非牺牲材料柱。 具有空气电介质的互连结构包括底部金属化层，顶部金属化层和分离底部和顶部金属化层并机械地支撑顶部金属化层的多个柱。 附加的类似互连结构可以堆叠在基底互连结构上。

公开(公告)号：US6054378A

公开(公告)日：2000-04-25

申请号：US104753

申请日：1998-06-25

Applicant: Stephen L. Skala ,  Subhas Bothra

Inventor： Stephen L. Skala ,  Subhas Bothra

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76843 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

Abstract: Disclosed is a method for encapsulating a via over a first metal layer of a semiconductor substrate in a damascene processing to prevent voiding. The method includes forming an intermetal oxide (IMO) layer over the first metal layer and forming a via in the IMO layer such that the via exposes a portion of the first metal layer and a side wall of the via in the IMO layer. The method also includes conformally forming a first barrier layer over the IMO layer and the via such that a portion of the first barrier layer is deposited over the side wall of the IMO layer and the exposed portion of the first metal layer. The method further includes depositing a second metal layer over the first barrier layer such that the second metal layer fills the via within the first barrier layer portion deposited in the via to form a metal via. Additionally, the method includes removing the second metal layer and the first barrier layer above a top portion of the IMO layer and forming a trench in a portion of the IMO layer in contact with the first barrier layer to a specified depth. The method further includes forming a second barrier layer in the trench. The method also forming a third metal layer over the second barrier layer in the trench to form a metal trench such that the metal via is encapsulated by the first barrier layer so as to reduce electromigration effect in the metal via.

Abstract translation: 公开了一种用于在大马士革处理中在半导体衬底的第一金属层上封装通孔以防止空隙的方法。 该方法包括在第一金属层上形成金属间氧化物（IMO）层，并在IMO层中形成通孔，使得通孔在IMO层中露出第一金属层的一部分和通孔的侧壁。 该方法还包括在IMO层和通孔上保形地形成第一阻挡层，使得第一阻挡层的一部分沉积在IMO层的侧壁和第一金属层的暴露部分上。 该方法还包括在第一阻挡层上沉积第二金属层，使得第二金属层填充沉积在通孔中的第一势垒层部分内的通孔以形成金属通孔。 此外，该方法包括在IMO层的顶部上方去除第二金属层和第一阻挡层，并在与第一阻挡层接触的IMO层的一部分中形成沟槽至特定深度。 该方法还包括在沟槽中形成第二阻挡层。 该方法还在沟槽中的第二阻挡层上形成第三金属层以形成金属沟槽，使得金属通孔被第一阻挡层封装，以便降低金属通孔中的电迁移效应。

公开(公告)号：US6046102A

公开(公告)日：2000-04-04

申请号：US196481

申请日：1998-11-19

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/4763 ,  H01L21/31

CPC classification number: H01L23/564 ,  H01L23/291 ,  H01L2924/0002

Abstract: Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositing a first silicon nitride barrier layer having a second thickness over the substrate and the metallization line. The method further including applying an oxide material over the first silicon nitride barrier layer that overlies the substrate and the metallization line. The oxide application includes a deposition component and a sputtering component, and the sputtering component is configured to remove at least a part of an edge of the first silicon nitride layer. The edge is defined by the metallization line underlying the first silicon nitride layer. Further, the method includes depositing a second silicon nitride layer over the oxide material that is applied by the deposition component and the edge of the first silicon nitride layer sputtered by the sputtering component to establish a moisture and mobile ion repelling barrier between the second and first silicon nitride layers.

Abstract translation: 公开了一种制备钝化涂层半导体结构的方法。 该方法包括提供具有在衬底上图案化的金属化线的衬底。 金属化线限定具有第一厚度的至少一个互连特征，以及在衬底和金属化线上沉积具有第二厚度的第一氮化硅阻挡层。 所述方法还包括在覆盖在衬底和金属化线上的第一氮化硅阻挡层上施加氧化物材料。 氧化物应用包括沉积部件和溅射部件，并且溅射部件被配置为去除第一氮化硅层的边缘的至少一部分。 边缘由第一氮化硅层下面的金属化线限定。 此外，该方法包括在由沉积部件施加的氧化物材料上沉积第二氮化硅层和由溅射部件溅射的第一氮化硅层的边缘，以在第二和第一之间建立湿气和可移动的离子排斥势垒 氮化硅层。

公开(公告)号：US6030885A

公开(公告)日：2000-02-29

申请号：US844076

申请日：1997-04-18

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L21/301 ,  H01L21/78

CPC classification number: H01L21/78

Abstract: The present invention provides for a hexagonal semiconductor die, semiconductor substrates and methods of forming a semiconductor die. One embodiment of the present invention provides a method of forming a semiconductor die comprising: providing a semiconductor wafer; forming an array of regular hexagonal dies upon the wafer, the array being formed in a two-dimensional honeycomb configuration; forming circuitry upon individual ones of the hexagonal dies; separating the hexagonal dies by laser cutting; and attaching a plurality of electrical contacts to the circuitry of individual ones of the hexagonal dies.

Abstract translation: 本发明提供六边形半导体管芯，半导体衬底以及形成半导体管芯的方法。 本发明的一个实施例提供一种形成半导体管芯的方法，包括：提供半导体晶片; 在所述晶片上形成正六边形晶粒的阵列，所述阵列以二维蜂窝结构形成; 在六角形模具的单独的一个上形成电路; 通过激光切割分离六边形模具; 以及将多个电触点附接到所述六边形模具中的单个电路的电路。

公开(公告)号：US6028013A

公开(公告)日：2000-02-22

申请号：US306239

申请日：1999-05-06

Applicant: Rao V. Annapragada ,  Samuel Vance Dunton ,  Milind Ganesh Weling ,  Subhas Bothra

Inventor： Rao V. Annapragada ,  Samuel Vance Dunton ,  Milind Ganesh Weling ,  Subhas Bothra

IPC: H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/44

CPC classification number: H01L21/02129 ,  H01L21/02131 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/31053 ,  H01L21/76819

Abstract: A method of making an inter-metal oxide layer over a patterned metallization layer of a substrate, and the resulting structure having the inter-metal oxide layer are provided. The method includes depositing a fluorine doped high density plasma (HDP) oxide layer over the patterned metallization layer. The fluorine doped HDP oxide layer is configured to evenly deposit in high aspect ratio regions of the patterned metallization layer. The method also includes depositing a plasma enhanced chemical vapor deposition (PECVD) oxide layer over the fluorine doped HDP oxide layer. The PECVD oxide layer is doped with a phosphorous material. A CMP operation is then performed over the PECVD oxide layer to remove topographical oxide variations, such that the CMP operation will be configured to preferably leave at least a coating of the PECVD oxide layer over the HDP oxide layer. In this example, the phosphorous material in the PECVD oxide is configured to assist in creating a substantial moisture barrier over the fluorine doped HDP oxide layer and thus protect metallization lines from corrosion. In an alternative example, a non-conductive, highly moisture resistant barrier layer can be deposited in between the fluorine doped HDP oxide layer and the PECVD oxide.

Abstract translation: 提供了在衬底的图案化金属化层上形成金属间氧化物层的方法，并且提供了所得到的具有金属间氧化物层的结构。 该方法包括在图案化的金属化层上沉积氟掺杂的高密度等离子体（HDP）氧化物层。 氟掺杂的HDP氧化物层被配置为均匀沉积在图案化金属化层的高纵横比区域中。 该方法还包括在氟掺杂的HDP氧化物层上沉积等离子体增强化学气相沉积（PECVD）氧化物层。 PECVD氧化物层掺杂有磷材料。 然后在PECVD氧化物层上执行CMP操作以去除形貌氧化物变化，使得CMP操作将被配置为优选地将PECVD氧化物层的至少一层涂层留在HDP氧化物层上。 在该实施例中，PECVD氧化物中的磷材料被配置成有助于在氟掺杂的HDP氧化物层上产生显着的湿气阻挡层，从而保护金属化线不受腐蚀。 在替代实例中，可以在氟掺杂的HDP氧化物层和PECVD氧化物之间沉积非导电，高度防潮的阻挡层。

公开(公告)号：US6013536A

公开(公告)日：2000-01-11

申请号：US838020

申请日：1997-04-22

Applicant: Edward D. Nowak ,  Subhas Bothra

Inventor： Edward D. Nowak ,  Subhas Bothra

IPC: H01L23/528 ,  G01R31/26 ,  H01L21/66

CPC classification number: H01L23/528 ,  H01L2924/0002

Abstract: Disclosed is a method for automating support pillar design in air dielectric interconnect structures. The method includes selecting features having an interconnect dimension from a first mask. Providing an intermediate support pattern defining a pillar spacing. Identifying overlap regions where the features selected from the first mask overlap the intermediate support pattern. The method further including filtering the overlap regions to eliminate features that are less than the interconnect dimension. The filtering being configured to define discrete pillar locations associated with the first mask.

Abstract translation: 公开了一种在空气介电互连结构中自动化支柱设计的方法。 该方法包括从第一掩模中选择具有互连尺寸的特征。 提供限定柱间距的中间支撑图案。 识别从第一掩模中选择的特征与中间支持图案重叠的重叠区域。 该方法还包括对重叠区域进行滤波以消除小于互连尺寸的特征。 所述过滤被配置为定义与所述第一掩模相关联的分立柱位置。

公开(公告)号：US5965941A

公开(公告)日：1999-10-12

申请号：US734501

申请日：1996-10-21

Applicant: Milind G. Weling ,  Subhas Bothra ,  Calvin T. Gabriel

Inventor： Milind G. Weling ,  Subhas Bothra ,  Calvin T. Gabriel

IPC: H01L21/3105 ,  H01L23/48 ,  H01L23/58 ,  H01L29/00

CPC classification number: H01L21/31053 ,  Y10S438/926

Abstract: A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

Abstract translation: 公开了用于不同层的半导体晶片的形貌图案密度的方法，以改进在晶片处理期间使用的化学机械抛光工艺。 为了实现晶片表面上的预定图案形状密度，根据需要将虚拟凸起线插入到迹线层上的有源导电迹线之间的间隙中。 在一些实施例中，预定图案密度在大约40％至80％的范围内。 在一些应用中，有源导电迹线和虚拟凸起线都是由金属材料形成的，该金属材料在化学机械抛光过程之前沉积在一个单一步骤中，绝缘层沉积在两个有源导电迹线和虚拟凸起线上 。 在其他应用中，假凸起线由绝缘层形成。