公开(公告)号：US11276730B2

公开(公告)日：2022-03-15

申请号：US16246360

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Christopher Wiegand ,  Tofizur Rahman ,  Noriyuki Sato ,  Gary Allen ,  James Pellegren ,  Angeline Smith ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Benjamin Buford ,  Ian Young

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/14 ,  H01L43/08 ,  H01L43/10

Abstract: A perpendicular spin orbit memory device includes a first electrode having a magnetic material and platinum and a material layer stack on a portion of the first electrode. The material layer stack includes a free magnet, a fixed magnet above the first electrode, a tunnel barrier between the free magnet and the fixed magnet and a second electrode coupled with the fixed magnet.

公开(公告)号：US11251186B2

公开(公告)日：2022-02-15

申请号：US16827542

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Noriyuki Sato ,  Sarah Atanasov ,  Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Ram Krishnamurthy ,  Hui Jae Yoo ,  Van H. Le

IPC: G11C11/24 ,  H01L27/108 ,  H01L27/12 ,  G11C11/4096

Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

公开(公告)号：US20200343301A1

公开(公告)日：2020-10-29

申请号：US16396451

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Benjamin Buford ,  Angeline Smith ,  Noriyuki Sato ,  Tanay Gosavi ,  Kaan Oguz ,  Christopher Wiegand ,  Kevin O'Brien ,  Tofizur Rahman ,  Gary Allen ,  Sasikanth Manipatruni ,  Emily Walker

IPC: H01L27/22 ,  H01L43/14 ,  H01L43/08 ,  H01L43/06 ,  H01L43/04

Abstract: A memory apparatus includes a first electrode having a spin orbit material. The memory apparatus further includes a first memory device on a portion of the first electrode and a first dielectric adjacent to a sidewall of the first memory device. The memory apparatus further includes a second memory device on a portion of the first electrode and a second dielectric adjacent to a sidewall of the second memory device. A second electrode is on and in contact with a portion of the first electrode, where the second electrode is between the first memory device and the second memory device. The second electrode has a lower electrical resistance than an electrical resistance of the first electrode. The memory apparatus further includes a first interconnect structure and a second interconnect, each coupled with the first electrode.

公开(公告)号：US20200005861A1

公开(公告)日：2020-01-02

申请号：US16022547

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Brian Doyle ,  Kaan Oguz ,  Noriyuki Sato ,  Charles Kuo ,  Mark Doczy

IPC: G11C11/56 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster comprises a magnetic material layer. The booster may further comprise an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to store 2 bits/cell.

公开(公告)号：US20190305216A1

公开(公告)日：2019-10-03

申请号：US15942231

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Ian Young ,  Kevin O'Brien ,  Gary Allen ,  Noriyuki Sato

IPC: H01L43/10 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  G11C11/16 ,  H01L27/22

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization; an interconnect adjacent to the magnetic junction, wherein the interconnect comprises an antiferromagnetic (AFM) material which is doped with a doping material (Pt, Ni, Co, or Cr) and a structure adjacent to the interconnect such that the magnetic junction and the structure are on opposite surfaces of the interconnect, wherein the structure comprises a magnet with a second magnetization substantially different from the first magnetization.

公开(公告)号：US12148734B2

公开(公告)日：2024-11-19

申请号：US17117350

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot Tan ,  Hui Jae Yoo ,  Noriyuki Sato ,  Travis W. Lajoie ,  Van H. Le ,  Thoe Michaelos

IPC: H01L25/065 ,  H10B12/00 ,  H10B10/00 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20 ,  H10B63/00

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

公开(公告)号：US12027458B2

公开(公告)日：2024-07-02

申请号：US17841551

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53209

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US11626451B2

公开(公告)日：2023-04-11

申请号：US16442767

申请日：2019-06-17

Applicant: INTEL CORPORATION

Inventor： Emily Walker ,  Carl H. Naylor ,  Kaan Oguz ,  Kevin L. Lin ,  Tanay Gosavi ,  Christopher J. Jezewski ,  Chia-Ching Lin ,  Benjamin W. Buford ,  Dmitri E. Nikonov ,  John J. Plombon ,  Ian A. Young ,  Noriyuki Sato

IPC: H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetic memory device comprising a plurality of memory cells is disclosed. The memory device includes an array of memory cells where each memory cell includes a first material layer having a ferromagnetic material, a second material layer having ruthenium, and a third material layer having bismuth and/or antimony. The second material layer is sandwiched between the first material layer and the third material in a stacked configuration.

公开(公告)号：US11594673B2

公开(公告)日：2023-02-28

申请号：US16367129

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Angeline Smith ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Benjamin Buford ,  Tofizur Rahman ,  Rohan Patil ,  Nafees Kabir ,  Michael Christenson ,  Ian Young ,  Hui Jae Yoo ,  Christopher Wiegand

IPC: H01F10/32 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

公开(公告)号：US11476412B2

公开(公告)日：2022-10-18

申请号：US16012672

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Noriyuki Sato ,  Kevin O'Brien ,  Benjamin Buford ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young

IPC: H01L43/04 ,  H01L43/10 ,  H01L43/08 ,  G11C11/16 ,  G11C11/18 ,  H01F10/32 ,  B82Y25/00

Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.