公开(公告)号：US20200006504A1

公开(公告)日：2020-01-02

申请号：US16022502

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Rishabh MEHANDRU ,  Anupama BOWONDER ,  Biswajeet GUHA ,  Anand MURTHY ,  Tahir GHANI

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a contact etch stop layer are described. In an example, an integrated circuit structure includes a fin including a semiconductor material, the fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures including a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer.

公开(公告)号：US20190252525A1

公开(公告)日：2019-08-15

申请号：US16396088

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/7782 ,  H01L29/78 ,  H01L29/785

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20180226478A1

公开(公告)日：2018-08-09

申请号：US15747719

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Uygar E. AVCI ,  David L. KENCKE ,  Patrick MORROW ,  Kerryann FOLEY ,  Stephen M. CEA ,  Rishabh MEHANDRU

IPC: H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/785

Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.

公开(公告)号：US20180219075A1

公开(公告)日：2018-08-02

申请号：US15747119

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20180219012A1

公开(公告)日：2018-08-02

申请号：US15747692

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Donald W. NELSON ,  Stephen M. CEA

IPC: H01L27/108

CPC classification number: H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/1087

Abstract: Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.

公开(公告)号：US20180212023A1

公开(公告)日：2018-07-26

申请号：US15745417

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Cory E. WEBER ,  Rishabh MEHANDRU ,  Stephen M. CEA

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L29/0673 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/66545

Abstract: Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.

公开(公告)号：US20240162141A1

公开(公告)日：2024-05-16

申请号：US18419015

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Aaron LILAK ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Rishabh MEHANDRU

IPC: H01L23/522 ,  H01L21/8234 ,  H01L25/16 ,  H01L29/06

CPC classification number: H01L23/5226 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823481 ,  H01L25/16 ,  H01L29/0653

Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

公开(公告)号：US20240006489A1

公开(公告)日：2024-01-04

申请号：US18367843

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Rishabh MEHANDRU ,  Willy RACHMADY ,  Harold KENNEL ,  Tahir GHANI

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/02356 ,  H01L21/02592 ,  H01L21/823871 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823807

Abstract: A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.

公开(公告)号：US20230317822A1

公开(公告)日：2023-10-05

申请号：US17711434

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Stephen M. CEA ,  Borna OBRADOVIC ,  Rishabh MEHANDRU ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/66553 ,  H01L29/66545 ,  H01L29/0673 ,  H01L29/0847

Abstract: Embodiments described herein may be related to transistor structures where dimpled spacers, which may also be referred to as inner spacers or offset spacers, may be formed around gates within an epitaxial structure such that the epitaxial material adjacent to the dimpled spacer is uniform and/or defect free. In embodiments, forming the dimpled spacers occurs after epitaxial growth. Other embodiments may be described and/or claimed.

公开(公告)号：US20230317786A1

公开(公告)日：2023-10-05

申请号：US17700215

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Cory WEBER ,  Varun MISHRA ,  Tahir GHANI ,  Pratik PATEL ,  Wonil CHUNG ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439

Abstract: Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.