公开(公告)号：US20180331191A1

公开(公告)日：2018-11-15

申请号：US15777140

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/765

CPC classification number: H01L29/404 ,  H01L21/765 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78

Abstract: Embodiments of the invention include a high voltage transistor with one or more field plates and methods of forming such transistors. According to an embodiment, the transistor may include a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region. Embodiments of the invention may also include a first interlayer dielectric (ILD) formed over the channel region and a second ILD formed over the first ILD. According to an embodiment, a first field plate may be formed in the second ILD. In an embodiment the first field plate is not formed as a single bulk conductive feature with the gate electrode. In some embodiments, the first field plate may be electrically coupled to the gate electrode by one or more vias. In alternative embodiments, the first field plate may be electrically isolated from the gate electrode.

公开(公告)号：US20180323298A1

公开(公告)日：2018-11-08

申请号：US15773422

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/08 ,  H01L29/20 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7788 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/78

Abstract: III-N transistor including a vertically-oriented lightly-doped III-N drift region between an overlying III-N 2DEG channel and an underlying heavily-doped III-N drain. In some embodiments, the III-N transistors are disposed over a silicon substrate. In some embodiments, lateral epitaxial overgrowth is employed to form III-N islands self-aligned with the vertically-oriented drift region. A gate electrode disposed over a portion of a III-N island may modulate a 2DEG within a channel region of the III-N island disposed above the III-N drift region. Charge carriers in the 2DEG channel may be swept into the drift region toward the drain. Topside contacts to each of the gate, source, and drain may be pitch scaled independently of a length of the drift region.

公开(公告)号：US20170236936A1

公开(公告)日：2017-08-17

申请号：US15499794

申请日：2017-04-27

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert S. CHAU ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Sanaz GARDNER ,  Ravi PILLARISETTY

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/10 ,  H01L29/205 ,  H01L21/762 ,  H01L29/34 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/7624 ,  H01L21/845 ,  H01L27/0605 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/66522

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

公开(公告)号：US20170077281A1

公开(公告)日：2017-03-16

申请号：US15122627

申请日：2014-06-13

Applicant: INTEL CORPORATION

Inventor： Kimin JUN ,  Sansaptak DASGUPTA ,  Alejandro X. LEVANDER ,  Patrick MORROW

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/04 ,  H01L29/20 ,  H01L29/66 ,  H01L21/78

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/76254 ,  H01L21/7806 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

Abstract translation: 一种包括在牺牲基板上的极性化合物半导体层上形成阻挡层的方法; 将牺牲衬底耦合到载体衬底以形成其中阻挡层设置在极性化合物半导体层和载体衬底之间的复合结构; 将牺牲衬底与复合结构分离以暴露极化合物半导体层; 以及形成至少一个电路装置。 一种在基板上包括阻挡层的装置; 阻挡层上的晶体管器件; 以及设置在所述阻挡层和所述晶体管器件之间的极性化合物半导体层，所述极性化合物半导体层包含二维电子气。

公开(公告)号：US20170012117A1

公开(公告)日：2017-01-12

申请号：US15120496

申请日：2014-03-21

Applicant: INTEL CORPORATION

Inventor： Marko RADOSAVLJEVIC ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Niloy MUKHERJEE ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L21/8256 ,  H01L29/66 ,  H01L27/12 ,  H01L29/24 ,  H01L21/02

CPC classification number: H01L29/7782 ,  H01L21/02422 ,  H01L21/02568 ,  H01L21/8256 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/0843 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78681

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the transistor channel may be disposed between the second barrier and the first barrier, and a bandgap of the transistor channel may be less than a bandgap of the first barrier and less than a bandgap of the second barrier. Other embodiments may be disclosed and/or claimed.

Abstract translation: 本文公开了半导体组件的实施例以及相关的集成电路器件和技术。 在一些实施例中，半导体组件可以包括柔性衬底，由第一过渡金属二硫属元素（TMD）材料形成的第一阻挡层，由第二TMD材料形成的晶体管沟道和由第三TMD材料形成的第二阻挡层。 第一势垒可以设置在晶体管沟道和柔性衬底之间，晶体管沟道可以设置在第二栅极和第一势垒之间，晶体管沟道的带隙可能小于第一势垒的带隙，而小于 第二个屏障的带隙。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20160276438A1

公开(公告)日：2016-09-22

申请号：US15036406

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

Abstract translation: 公开了用于在具有多纵横比掩模的不同基板上形成无缺陷半导体结构的技术。 多纵横比掩模包括形成在基板上的第一，第二和第三层。 第二层分别具有比第一和第三层中的第一开口和第三开口更宽的第二开口。 所有三个开口沿着共同的中心轴线居中。 半导体材料从衬底的顶表面生长并横向放置在第二开口内的第一层的顶表面上。 通过使用第三层作为蚀刻掩模来蚀刻设置在第三开口内并垂直于第三开口下方的半导体材料，使得横向溢出到第一层的顶表面上的剩余材料形成剩余结构。

公开(公告)号：US20210167200A1

公开(公告)日：2021-06-03

申请号：US16645119

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/51 ,  H01L21/8252 ,  H01L29/40

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device that may include an III-V transistor with a resistive gate contact. A semiconductor device may include a substrate, and a channel base including a layer of GaN above the substrate. A channel stack may be above the channel base, and may include a layer of GaN in the channel stack, and a polarization layer above the layer of GaN in the channel stack. A gate stack may be above the channel stack, where the gate stack may include a gate dielectric layer above the channel stack, and a resistive gate contact above the gate dielectric layer. The resistive gate contact may include silicon (Si) or germanium (Ge). Other embodiments may be described and/or claimed.

公开(公告)号：US20200066893A1

公开(公告)日：2020-02-27

申请号：US16321722

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pavel M. AGABABOV

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor transistor structure is described. In an example, the semiconductor transistor includes a group III-N semiconductor material disposed on a doped buffer layer, above a substrate. A polarization charge inducing layer is disposed on and conformal with the sloped sidewalls and a planar uppermost surface of the group III-N semiconductor material. A gate structure is disposed on the sloped sidewalls. A source contact is formed on an uppermost portion of the polarization charge inducing layer. A drain region is formed adjacent to the doped buffer layer. An insulator layer is disposed on the drain region and separates the gate structure from the drain region.

公开(公告)号：US20200066890A1

公开(公告)日：2020-02-27

申请号：US16321789

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/08 ,  H01L29/205 ,  H01L29/45 ,  H01L29/66 ,  H01L29/861 ,  H01L27/06

Abstract: A transistor connected diode structure is described. In an example, the transistor connected diode structure includes a group III-N semiconductor material disposed on substrate. A raised source structure and a raised drain structure are disposed on the group III-N semiconductor material. A mobility enhancement layer is disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the mobility enhancement layer, the polarization charge inducing layer having a first portion and a second portion separated by a gap. A gate dielectric layer disposed on the mobility enhancement layer in the gap. A first metal electrode having a first portion disposed on the raised drain structure, a second portion disposed above the second portion of the polarization charge inducing layer and a third portion disposed on the gate dielectric layer in the gap. A second metal electrode disposed on the raised source structure.

公开(公告)号：US20200066849A1

公开(公告)日：2020-02-27

申请号：US16322453

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/20 ,  H01L29/868 ,  H01L29/66 ,  H01L29/205

Abstract: A P-i-N diode structure includes a group III-N semiconductor material disposed on a substrate. An n-doped raised drain structure is disposed on the group III-N semiconductor material. An intrinsic group III-N semiconductor material is disposed on the n-doped raised drain structure. A p-doped group III-N semiconductor material is disposed on the intrinsic group III-N semiconductor material. A first electrode is connected to the p-doped group III-N semiconductor material. A second electrode is electrically coupled to the n-doped raised drain structure. In an embodiment, a group III-N transistor is electrically coupled to the P-i-N diode. In an embodiment, a group III-N transistor is electrically isolated from the P-i-N diode. In an embodiment, a gate electrode and an n-doped raised drain structure are electrically coupled to the n-doped raised drain structure and the second electrode of the P-i-N diode to form the group III-N transistor.