公开(公告)号：US12266682B2

公开(公告)日：2025-04-01

申请号：US17025209

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mohammad Enamul Kabir ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L23/49 ,  H01L23/492 ,  H01L49/02

Abstract: Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.

公开(公告)号：US12062616B2

公开(公告)日：2024-08-13

申请号：US18377183

申请日：2023-10-05

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/075 ,  H01L25/16

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0753 ,  H01L25/167 ,  H01L2224/81 ,  H01L2924/181

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20240105577A1

公开(公告)日：2024-03-28

申请号：US17954174

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Zhenguo Jiang ,  Zhiguo Qian ,  Jiwei Sun ,  Babita Dhayal

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49866

Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit packages with grounding members are disclosed. An example semiconductor die disclosed herein includes a semiconductor substrate, metal interconnects proximate a first side of the semiconductor substrate, a metal contact proximate a second side of the semiconductor substrate opposite the first side, a first grounding member extending from a grounding interconnect of the metal interconnects to a first distal point in the semiconductor substrate, and a second grounding member extending from the metal contact to a second distal point in the semiconductor substrate, the first distal point closer to the first side of the semiconductor substrate than the second distal point is to the first side of the semiconductor substrate.

公开(公告)号：US11901280B2

公开(公告)日：2024-02-13

申请号：US17956766

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/486 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20240006289A1

公开(公告)日：2024-01-04

申请号：US17853204

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Kemal Aygun ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Zhiguo Qian ,  Jiwei Sun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01L23/552 ,  H01L21/4853 ,  H01L21/76877 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/3025

Abstract: An electronic device includes a substrate including a core layer having a first surface and a second surface opposite the first surface, and at least one coaxial through-hole extending vertically through the core layer from the first surface to the second surface. The coaxial through-hole includes at least a first through-via that includes electrically conductive material extending through the core layer from the first surface to the second surface, and a conductive layer including the same or different electrically conductive material extending vertically through the core layer from the first surface to the second surface and surrounding the first through-via. The conductive layer is to be connected to a ground voltage and is electrically isolated from the first through-via.

公开(公告)号：US20230420347A1

公开(公告)日：2023-12-28

申请号：US17847282

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Cemil Geyik ,  Zhiguo Qian ,  Kristof Kuwawi Darmawikarta ,  Zhichao Zhang ,  Kemal Aygun

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/4857 ,  H01L25/0652

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate having a first face and an opposing second face, the package substrate comprising a conductive trace in a dielectric material, a conductive structure at least partially surrounding the conductive trace and separated from the conductive trace by the dielectric material; and an integrated circuit (IC) die attached to the first face of the package substrate and coupled to the conductive trace by a conductive pathway through the package substrate. The conductive trace has a non-rectangular cross-section with rounded corners, the conductive structure comprises a plurality of conductive planes parallel to the conductive trace and coupled to a ground connection.

公开(公告)号：US11682613B2

公开(公告)日：2023-06-20

申请号：US17360701

申请日：2021-06-28

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kaladhar Radhakrishnan ,  Kemal Aygun

IPC: H01L23/49 ,  H01L23/64 ,  H01L23/498 ,  H01L21/68 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/68 ,  H01L23/49827 ,  H01L24/17 ,  H01L23/5384 ,  H01L2224/08165 ,  H01L2224/16157 ,  H01L2224/16165 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24221 ,  H01L2224/32165 ,  H01L2224/32235 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2924/30111

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US20230103183A1

公开(公告)日：2023-03-30

申请号：US17485045

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas V. Pietambaram ,  Kemal Aygun ,  Telesphor Kamgaing ,  Zhiguo Qian ,  Jiwei Sun

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48

Abstract: Glass substrates having signal shielding for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer defining a channel and a TGV. The channel at least partially surrounding the TGV. A signal transmission line is provided in the opening and extending through the core layer. An electrically conductive material positioned in the channel. The conductive material to provide electromagnetic shielding to the transmission line.

公开(公告)号：US20220399277A1

公开(公告)日：2022-12-15

申请号：US17345969

申请日：2021-06-11

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Scott E. Siers ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Zhiguo Qian ,  Kalyan C. Kolluru ,  Vivek Kumar Rajan ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: An Integrated Circuit (IC), comprising a first conductive trace on a first die, a second conductive trace on a second die, and a conductive pathway electrically coupling the first conductive trace with the second conductive trace. The second die is coupled to the first die with interconnects. The conductive pathway comprises a portion of the interconnects located proximate to a periphery of a region in the first die through which the first conductive trace is not routable. In some embodiments, the conductive pathway reroutes electrical connections away from the region. The region comprises a high congestion zone having high routing density in some embodiments. In other embodiments, the region comprises a “keep-out” zone.

公开(公告)号：US20220199537A1

公开(公告)日：2022-06-23

申请号：US17127304

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Peipei Wang ,  Daniel Krueger ,  Edward Burton

IPC: H01L23/538 ,  H01L23/50 ,  H01L25/065 ,  H01L21/50

Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.