Patent search ap:("INVENSAS CORPORATION") AND inv:"Cyprian Emeka Uzoh" Page 5

41.

发明申请
LOW COST INTERPOSER AND METHOD OF FABRICATION 有权
Title translation: 低成本插销器和制造方法

公开(公告)号：US20140263582A1

公开(公告)日：2014-09-18

申请号：US13830279

申请日：2013-03-14

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L21/64

CPC classification number: H01L21/64 , H01L21/486 , H01L23/49827 , H01L23/49861 , H01L2924/0002 , H01L2924/19107 , H01L2924/00

Abstract: A method for making an interposer is provided. A conductive layer is formed by contacting a replicate such that a shape of a surface of the conductive layer conforms to a shape of the contacted portion of the replicate. The conductive layer is formed to have a base and a plurality of conductive posts projecting away from the base. Each conductive post is formed to have a post end opposite the base. A dielectric layer is formed to cover the base and to separate adjacent ones of the posts from each other. The posts are for forming vias. Conductive material is removed from the conductive layer to insulate at least one post from at least one other post.

Abstract translation: 提供了一种制造插入件的方法。通过使重复接触形成导电层，使得导电层的表面的形状与复制体的接触部分的形状一致。导电层形成为具有基部和从基部突出的多个导电柱。每个导电柱形成为具有与基部相对的后端。形成介电层以覆盖基部并将相邻的柱彼此分开。这些岗位用于形成通孔。从导电层移除导电材料，以将至少一个柱与至少一个其他柱绝缘。

42.

发明申请
METHOD AND STRUCTURES FOR VIA SUBSTRATE REPAIR AND ASSEMBLY 有权
Title translation: 通过基板维修和组装的方法和结构

公开(公告)号：US20140159249A1

公开(公告)日：2014-06-12

申请号：US13711042

申请日：2012-12-11

Applicant: INVENSAS CORPORATION

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/498

CPC classification number: H01L23/481 , H01L21/76841 , H01L21/76843 , H01L21/76898 , H01L23/49827 , H01L2224/05647 , H01L2924/0002 , H01L2924/00

Abstract: A component can include a substrate having an opening extending between first and second surfaces thereof, and an electrically conductive via having first and second portions. The first portion can include a first layer structure extending within the opening and at least partially along an inner wall of the opening, and a first principal conductor extending within the opening and at least partially overlying the first layer structure. The first portion can be exposed at the first surface and can have a lower surface located between the first and second surfaces. The second portion can include a second layer structure extending within the opening and at least partially along the lower surface of the first portion, and a second principal conductor extending within the opening and at least partially overlying the second layer structure. The second portion can be exposed at the second surface.

Abstract translation: 组件可以包括具有在其第一和第二表面之间延伸的开口的基板和具有第一和第二部分的导电通孔。第一部分可以包括在开口内延伸并且至少部分地沿着开口的内壁延伸的第一层结构，以及在开口内延伸并且至少部分地覆盖第一层结构的第一主导体。第一部分可以在第一表面处露出并且可以具有位于第一和第二表面之间的下表面。第二部分可以包括在开口内延伸并且至少部分地沿着第一部分的下表面延伸的第二层结构，以及在开口内延伸并且至少部分地覆盖第二层结构的第二主导体。第二部分可以在第二表面露出。

43.

发明授权
Tall and fine pitch interconnects 有权

公开(公告)号：US10818629B2

公开(公告)日：2020-10-27

申请号：US16127696

申请日：2018-09-11

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh , Rajesh Katkar

IPC: H01L23/48 , H01L23/00 , H01L25/00 , H01L21/683 , H01L25/065 , H05K3/34

Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

44.

发明申请
Structures And Methods For Low Temperature Bonding Using Nanoparticles 审中-公开

公开(公告)号：US20200152598A1

公开(公告)日：2020-05-14

申请号：US16740670

申请日：2020-01-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00 , H01L25/00 , H01L25/065

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

45.

发明授权
Method and apparatus for stacking devices in an integrated circuit assembly 有权

公开(公告)号：US10515838B2

公开(公告)日：2019-12-24

申请号：US16193679

申请日：2018-11-16

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L21/76 , H01L21/683 , H01L25/00 , H01L23/00 , H01L21/67 , H01L25/065

Abstract: Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both top side processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that top sides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks.

46.

发明授权
Anchoring structure of fine pitch bva 有权

公开(公告)号：US10332854B2

公开(公告)日：2019-06-25

申请号：US15332533

申请日：2016-10-24

Applicant: Invensas Corporation

Inventor： Rajesh Katkar , Gabriel Z. Guevara , Xuan Li , Cyprian Emeka Uzoh , Guilian Gao , Liang Wang

IPC: H01L23/00 , H01L23/31 , H01L21/56 , H01L25/10 , H01L25/00

Abstract: A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.

47.

发明授权
Multiple bond via arrays of different wire heights on a same substrate 有权

公开(公告)号：US10290613B2

公开(公告)日：2019-05-14

申请号：US16008531

申请日：2018-06-14

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh , Rajesh Katkar

IPC: B81B7/00 , H01L21/48 , H01L23/00 , H01L23/42 , H01L23/48 , H01L25/00 , H01L25/16 , H01L49/02 , H01L23/367 , H01L23/498 , H01L23/522 , H01L23/538 , H01L25/065

Abstract: Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

48.

发明申请
HYBRID 3D/2.5D INTERPOSER 审中-公开

公开(公告)号：US20190096849A1

公开(公告)日：2019-03-28

申请号：US16197686

申请日：2018-11-21

Applicant: Invensas Corporation

Inventor： Charles G. Woychik , Cyprian Emeka Uzoh , Sangil Lee , Liang Wang , Guilian Gao

IPC: H01L25/065 , H01L25/00 , H01L21/48 , H01L23/00 , H01L23/31

Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.

49.

发明申请
INTERCONNECT STRUCTURES AND METHODS FOR FORMING SAME 审中-公开

公开(公告)号：US20190096741A1

公开(公告)日：2019-03-28

申请号：US16140995

申请日：2018-09-25

Applicant: INVENSAS CORPORATION

Inventor： Cyprian Emeka Uzoh , Laura Wills Mirkarimi

IPC: H01L21/768 , H01L23/532 , H01L23/522 , H01L23/00

Abstract: A method for forming an interconnect structure in an element is disclosed. The method can include patterning a cavity in a non-conductive material. The method can include exposing a surface of the cavity in the non-conductive material to a surface nitriding treatment. The method can include depositing a conductive material directly onto the treated surface after the exposing.