公开(公告)号：US20060202353A1

公开(公告)日：2006-09-14

申请号：US11429368

申请日：2006-05-05

申请人： Takeshi Wakabayashi ,  Ichiro Mihara

发明人： Takeshi Wakabayashi ,  Ichiro Mihara

IPC分类号： H01L23/48

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A plurality of semiconductor chips are bonded to an adhesive layer formed on a base plate. Then, first to third insulating films, first and second underlying metal layers, first and second re-wirings, and a solder ball are collectively formed for the plural semiconductor chips. In this case, the first and second underlying metal layers are formed by a sputtering method, and the first and second re-wirings are formed by an electroplating method. Then, a laminate structure consisting of the three insulating films, the adhesive layer, and the base plate is cut in a region positioned between the adjacent semiconductor chips.

摘要翻译： 多个半导体芯片被接合到形成在基板上的粘合剂层。 然后，对于多个半导体芯片，共同形成第一至第三绝缘膜，第一和第二下面的金属层，第一和第二重新布线以及焊球。 在这种情况下，通过溅射法形成第一和第二基底金属层，并且通过电镀方法形成第一和第二重新布线。 然后，在位于相邻的半导体芯片之间的区域中切割由三个绝缘膜，粘合剂层和基板组成的层叠结构。

公开(公告)号：US20050098891A1

公开(公告)日：2005-05-12

申请号：US10472803

申请日：2003-02-03

申请人： Takeshi Wakabayashi ,  Ichiro Mihara

发明人： Takeshi Wakabayashi ,  Ichiro Mihara

IPC分类号： H01L21/58 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L23/485

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A plurality of semiconductor chips (23) are bonded to an adhesive layer (22) formed on a base plate (21). Then, first to third insulating films (31, 35, 39), first and second underlying metal layers (33, 37), first and second re-wirings (34, 38), and a solder ball (41) are collectively formed for the plural semiconductor chips (23). In this case, the first and second underlying metal layers (33, 37) are formed by a sputtering method, and the first and second re-wirings (34, 38) are formed by an electroplating method. Then, a laminate structure consisting of the three insulating films (39, 35, 31), the adhesive layer (22), and the base plate (21) is cut in a region positioned between the adjacent semiconductor chips (23).

摘要翻译： 多个半导体芯片（23）被接合到形成在基板（21）上的粘合剂层（22）上。 然后，共同形成第一至第三绝缘膜（31,35,39），第一和第二下面的金属层（33,37），第一和第二重新布线（34,38）以及焊球（41） 多个半导体芯片（23）。 在这种情况下，通过溅射法形成第一和第二下面的金属层（33,37），并且通过电镀方法形成第一和第二重新布线（34,38）。 然后，在位于相邻的半导体芯片（23）之间的区域中切割由三个绝缘膜（39,35,31），粘合剂层（22）和基板（21）组成的层叠结构。

公开(公告)号：US20050084989A1

公开(公告)日：2005-04-21

申请号：US10964019

申请日：2004-10-12

申请人： Takeshi Wakabayashi ,  Ichiro Mihara

发明人： Takeshi Wakabayashi ,  Ichiro Mihara

IPC分类号： H01L21/66 ,  G01R31/28 ,  H01L21/56 ,  H01L23/12 ,  H01L23/31 ,  H01L23/485

CPC分类号： H01L24/10 ,  G01R31/2863 ,  G01R31/2886 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

摘要： After columnar electrodes and a sealing film are formed above a semiconductor substrate in a wafer state, probe pins are brought into contact with the upper surfaces of the columnar electrodes, and burn-in is executed. Next, solder balls are formed on the columnar electrodes, and the semiconductor substrate in a wafer state is diced. As a result, any unwanted deformation of the solder balls by contact of the probe pins can be prevented. In addition, even when the heights of the solder balls vary, burn-in can be performed.

摘要翻译： 在晶片状态的半导体基板的上方形成柱状电极和密封膜之后，使探针与柱状电极的上表面接触，进行老化。 接下来，在柱状电极上形成焊球，切割晶片状态的半导体基板。 结果，可以防止焊球通过探针的接触而引起的任何不希望的变形。 此外，即使当焊球的高度变化时，也可以进行老化。

公开(公告)号：US06870256B2

公开(公告)日：2005-03-22

申请号：US10254222

申请日：2002-09-25

申请人： Yutaka Aoki ,  Ichiro Mihara ,  Takeshi Wakabayashi ,  Katsumi Watanabe

发明人： Yutaka Aoki ,  Ichiro Mihara ,  Takeshi Wakabayashi ,  Katsumi Watanabe

IPC分类号： H01L21/3205 ,  H01L20060101 ,  H01L21/60 ,  H01L21/822 ,  H01L23/50 ,  H01L23/52 ,  H01L23/522 ,  H01L27/00 ,  H01L27/04 ,  H01L29/40 ,  H01L31/00

CPC分类号： H01L23/3114 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/00

摘要： In a semiconductor device, re-wiring is provided on a circuit element formation region of a semiconductor substrate. A columnar electrode for connection with a circuit board is provided on the rewiring. A first insulating film is provided over the semiconductor substrate excluding a connection pad, and a ground potential layer connected to a ground potential is provided on an upper surface of the first insulating film. A re-wiring is provided over the ground potential layer with a second insulating film interposed. The ground potential layer serves as a barrier layer for preventing crosstalk between the re-wiring and circuit element formation region. A thin-film circuit element is provided on the second insulating film, and a second ground potential layer is provided as a second barrier layer over the thin-film circuit element with an insulating film interposed. Re-wiring is provided over the second ground potential layer.

摘要翻译： 在半导体器件中，在半导体衬底的电路元件形成区域上设置再布线。 在重新布线时提供用于与电路板连接的柱状电极。 第一绝缘膜设置在除了连接焊盘之外的半导体衬底上，并且在第一绝缘膜的上表面上设置连接到接地电位的接地电位层。 在地电位层上提供再布线，其中插入有第二绝缘膜。 地电位层用作防止重新布线和电路元件形成区域之间的串扰的阻挡层。 薄膜电路元件设置在第二绝缘膜上，第二接地电位层设置在薄膜电路元件上，作为第二阻挡层，绝缘膜被插入。 在第二接地电位层上提供重新布线。

公开(公告)号：US20050051886A1

公开(公告)日：2005-03-10

申请号：US10916917

申请日：2004-08-12

申请人： Ichiro Mihara ,  Takeshi Wakabayashi ,  Toshihiro Kido ,  Hiroyasu Jobetto ,  Yutaka Yoshino ,  Nobuyuki Kageyama ,  Daita Kohno ,  Jun Yoshizawa

发明人： Ichiro Mihara ,  Takeshi Wakabayashi ,  Toshihiro Kido ,  Hiroyasu Jobetto ,  Yutaka Yoshino ,  Nobuyuki Kageyama ,  Daita Kohno ,  Jun Yoshizawa

IPC分类号： H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L23/16 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.

摘要翻译： 半导体器件包括至少一个半导体结构，其具有形成在半导体衬底上的多个外部连接电极。 在半导体结构的一侧设置有绝缘片部件。 上部互连具有连接焊盘部分，其布置在与上部互连件对应并且连接到半导体结构的外部连接电极的绝缘片部件上。

公开(公告)号：US6140155A

公开(公告)日：2000-10-31

申请号：US459019

申请日：1999-12-10

申请人： Ichiro Mihara ,  Shoichi Kotani ,  Takeshi Wakabayashi ,  Masami Hiramoto

发明人： Ichiro Mihara ,  Shoichi Kotani ,  Takeshi Wakabayashi ,  Masami Hiramoto

IPC分类号： H01L21/60 ,  H01L21/68 ,  H01L23/485 ,  H01L24/50

CPC分类号： H01L21/6835 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68313 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14

摘要： A plating tray includes a recessed region in a central portion of an insulating substrate for arranging therein a silicon semiconductor substrate and a metal film arranged to surround the recessed region. The semiconductor substrate is housed in the recessed region. Under this condition, a dry photoresist film containing Na, K, Ca and Cu in amounts smaller than predetermined amounts is formed to cover a metal underlying film. Then, a projecting electrode is formed by electroplating within open portions formed in the resist film. In forming the projecting electrode, the open portion is also formed in that region of the resist film which corresponds to the metal film of the plating plate so as to form a dummy projection electrode simultaneously.

摘要翻译： 电镀托盘包括在绝缘基板的中心部分中的凹陷区域，用于在其中布置硅半导体衬底和布置成围绕凹陷区域的金属膜。 半导体衬底容纳在凹陷区域中。 在这种条件下，形成含有小于预定量的Na，K，Ca和Cu的干的光致抗蚀剂膜以覆盖金属底层膜。 然后，通过在形成在抗蚀剂膜上的开口部内进行电镀而形成突出电极。 在形成突出电极时，开口部也形成在对应于电镀板的金属膜的抗蚀剂膜的区域中，以同时形成虚设的投影电极。

公开(公告)号：US20070126127A1

公开(公告)日：2007-06-07

申请号：US11671268

申请日：2007-02-05

申请人： Hiroyasu Jobetto ,  Ichiro Mihara

发明人： Hiroyasu Jobetto ,  Ichiro Mihara

IPC分类号： H01L23/48

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24227 ,  H01L2224/24247 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/83 ,  H01L2224/85399 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate and has openings for exposing the connection pads, and conductors which are connected to the connection pads, arranged on the protective layer, and have pads. An upper insulating layer covers the entire upper surface of the semiconductor construction assembly including the conductors except the pads. A sealing member covers at least one side surface of the semiconductor construction assembly. An upper conductors is formed on the upper insulating layer, and has one ends electrically connected to the pads and an external connection pads, respectively, an external connection pad of at least one of the upper conductors being disposed in a region corresponding to the sealing member.

公开(公告)号：US07112469B2

公开(公告)日：2006-09-26

申请号：US11037423

申请日：2005-01-18

申请人： Ichiro Mihara

发明人： Ichiro Mihara

IPC分类号： H01L21/50

CPC分类号： H01L24/24 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

摘要： A semiconductor device includes a base member made of a material containing at least a thermosetting resin, and at least one semiconductor constructing body mounted on the base member, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base member around the semiconductor constructing body. An interconnection of at least one layer is formed on one sides of the semiconductor constructing body and insulating layer, electrically connected to the external connecting electrode of the semiconductor constructing body, and having a connecting pad portion, the semiconductor substrate is fixed to the base member by fixing force of the base member.

摘要翻译： 一种半导体器件包括由至少含有热固性树脂的材料制成的基底构件和安装在基底构件上的至少一个半导体构造体，并且具有形成在半导体衬底上的半导体衬底和多个外部连接电极。 在半导体构造体周围的基底构件上形成绝缘层。 至少一层的互连形成在与半导体构造体的外部连接电极电连接的半导体构造体和绝缘层的一侧上，并且具有连接焊盘部分，半导体衬底固定到基底构件 通过基体的固定力。

公开(公告)号：US06467674B1

公开(公告)日：2002-10-22

申请号：US09722943

申请日：2000-11-27

申请人： Ichiro Mihara

发明人： Ichiro Mihara

IPC分类号： H01L214763

CPC分类号： H01L21/56 ,  H01L23/3171 ,  H01L24/03 ,  H01L2224/0401

摘要： A sealing film is formed on a semiconductor substrate on which a number of columnar electrodes are formed, and then the upper surface of the sealing film is polished to expose the upper surfaces of the columnar electrodes made of a soft metal. During the polishing, laterally broadened edges are generated on the upper sides of the columnar electrodes. Then, the upper surfaces of the columnar electrodes, including the laterally broadened edges, are etched so as to remove the edges. In this manner, the shape of the upper surfaces of the columnar electrodes can be formed as initially designed, and therefore the bonding strengths can be made uniform. Thus, the reliability of the device can be improved.

摘要翻译： 在其上形成有多个柱状电极的半导体基板上形成密封膜，然后对密封膜的上表面进行抛光以露出由软金属制成的柱状电极的上表面。 在抛光期间，在柱状电极的上侧产生横向变宽的边缘。 然后，蚀刻包括横向变宽的边缘的柱状电极的上表面，以便去除边缘。 以这种方式，柱状电极的上表面的形状可以如初步设计的那样形成，因此能够使接合强度均匀。 因此，可以提高装置的可靠性。

公开(公告)号：US06319851B1

公开(公告)日：2001-11-20

申请号：US09487165

申请日：2000-01-19

申请人： Ichiro Mihara ,  Osamu Kuwabara

发明人： Ichiro Mihara ,  Osamu Kuwabara

IPC分类号： H01L2131

CPC分类号： H01L21/56 ,  H01L2224/274 ,  H01L2924/10253 ,  Y10S438/942 ,  Y10S438/945 ,  H01L2924/00

摘要： A resin sealing film is formed on a silicon substrate by using a printing mask and a squeegee. The side surface in the tip portion of the squeegee is substantially V-shaped, and the printing is performed by pushing the tip portion of the squeegee into the gap between adjacent bump electrodes. As a result, the sealing film is formed in a manner to be depressed in the region between adjacent bump electrodes so as to facilitate the swinging movement of the bump electrodes. It follows that, in a temperature cycle test performed after the silicon substrate is mounted to a circuit substrate, the stress derived from the difference in thermal expansion coefficient between the silicon substrate and the circuit substrate is absorbed by the bump electrode.

摘要翻译： 通过使用印刷掩模和刮板在硅基板上形成树脂密封膜。 刮板的前端部的侧面大致呈V字状，通过将刮板的前端部推入相邻的凸块电极间的间隙来进行印刷。 结果，密封膜以相邻凸起电极之间的区域被压下的方式形成，以便于凸起电极的摆动。 因此，在将硅衬底安装到电路衬底之后执行的温度循环测试中，由硅衬底和电路衬底之间的热膨胀系数差导致的应力被凸块电极吸收。