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    ADAPTIVE ROUTING FOR POOLED AND TIERED DATA ARCHITECTURES
    43.
    发明申请
    ADAPTIVE ROUTING FOR POOLED AND TIERED DATA ARCHITECTURES 有权

    公开(公告)号：US20250086123A1

    公开(公告)日：2025-03-13

    申请号：US18894967

    申请日：2024-09-24

    Applicant: Intel Corporation

    Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT

    IPC: G06F12/14 ,  G06F12/06 ,  G06F12/0813 ,  G06F12/0891

    Abstract: In an embodiment, network device apparatus is provided that includes packet processing circuitry to determine if target data associated with a memory access request is stored in a different device than that identified in the memory access request, and based on the target data associated with the memory access request identified as stored in a different device than that identified in the memory access request, may cause transmission of the memory access request to the different device. The memory access request may comprise an identifier of a requester of the memory access request and the identifier may comprise a Process Address Space identifier (PASID).

    SELECTION OF PRIMARY AND SECONDARY MANAGEMENT CONTROLLERS IN A MULTIPLE MANAGEMENT CONTROLLER SYSTEM
    45.
    发明公开
    SELECTION OF PRIMARY AND SECONDARY MANAGEMENT CONTROLLERS IN A MULTIPLE MANAGEMENT CONTROLLER SYSTEM 审中-公开

    公开(公告)号：US20230375994A1

    公开(公告)日：2023-11-23

    申请号：US18228547

    申请日：2023-07-31

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT ,  Eoin WALSH ,  Karthik KUMAR ,  Marcos E. CARRANZA

    IPC: G05B19/042

    CPC classification number: G05B19/042 ,  G05B2219/2214 ,  G05B2219/25022

    Abstract: Examples described herein relate to a system. In some examples, the system includes an interface and circuitry, coupled to the interface. In some examples, the circuitry, when operational, is to: based on detection of multiple management controllers, select a primary management controller and a secondary management controller from among the multiple management controllers. In some examples, the primary management controller is to perform at least one different operation than that of the secondary management controller, the primary management controller comprises a baseboard management controller (BMC), the secondary management controller comprises a BMC, and the multiple management controllers are positioned in at least one programmable network interface device and a host system.

    RAS (RELIABILITY, AVAILABILITY, AND SERVICEABILITY)-BASED MEMORY DOMAINS
    46.
    发明公开
    RAS (RELIABILITY, AVAILABILITY, AND SERVICEABILITY)-BASED MEMORY DOMAINS 审中-公开

    公开(公告)号：US20230222025A1

    公开(公告)日：2023-07-13

    申请号：US18124453

    申请日：2023-03-21

    Applicant: Intel Corporation

    Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT ,  Mark A. SCHMISSEUR ,  Thomas WILLHALM ,  Marcos E. CARRANZA

    IPC: G06F11/00 ,  G06F11/14

    CPC classification number: G06F11/008 ,  G06F11/142

    Abstract: Reliability, availability, and serviceability (RAS)-based memory domains can enable applications to store data in memory domains having different degrees of reliability to reduce downtime and data corruption due to memory errors. In one example, memory resources are classified into different RAS-based memory domains based on their expected likelihood of encountering errors. The mapping of memory resources into RAS-based memory domains can be dynamically managed and updated when information indicative of reliability (such as the occurrence of errors or other information) suggests that a memory resource is becoming less reliable. The RAS-based memory domains can be exposed to applications to enable applications to allocate memory in high reliability memory for critical data.

    METHOD AND APPARATUS TO SELECT ASSIGNABLE DEVICE INTERFACES FOR VIRTUAL DEVICE COMPOSITION
    47.
    发明申请
    METHOD AND APPARATUS TO SELECT ASSIGNABLE DEVICE INTERFACES FOR VIRTUAL DEVICE COMPOSITION 有权

    公开(公告)号：US20230004417A1

    公开(公告)日：2023-01-05

    申请号：US17903327

    申请日：2022-09-06

    Applicant: Intel Corporation

    Inventor： Karthik V. NARAYANAN ,  Raghunathan SRINIVASAN ,  Karthik KUMAR

    IPC: G06F9/455 ,  G06F9/54

    Abstract: Scalable I/O Virtualization (Scalable IOV) allows efficient and scalable sharing of Input/Output (I/O) devices across a large number of containers or Virtual Machines. Scalable IOV defines the granularity of sharing of a device as an Assignable Device Interface (ADI). In response to a request for a virtual device composition, an ADI is selected based on affinity to the same NUMA node as the running virtual machine, utilization metrics for the Input-Output Memory Management Unit (IOMMU) unit and utilization metrics of a device of a same device class. Selecting the ADI based on locality and utilization metrics reduces latency and increases throughput for a virtual machine running critical or real-time workloads.

    SOFTWARE-ASSISTED SPARSE MEMORY
    49.
    发明申请
    SOFTWARE-ASSISTED SPARSE MEMORY 有权

    公开(公告)号：US20220318132A1

    公开(公告)日：2022-10-06

    申请号：US17847026

    申请日：2022-06-22

    Applicant: Intel Corporation

    Inventor： Thomas WILLHALM ,  Francesc GUIM BERNAT ,  Karthik KUMAR

    IPC: G06F12/02

    Abstract: Methods and apparatus for software-assisted sparse memory. A processor including a memory controller is configured to implement one or more portions of the memory space for memory accessed via the memory controller as sparse memory regions. The amount of physical memory used for a sparse memory region is a fraction of the address range for the sparse memory region, where only non-zero data are written to the physical memory. Mechanisms are provided to detect memory access requests for memory in a sparse memory region and perform associated operations, while non-sparse memory access operations are performed when accessing memory that is not in a sparse memory region. Interfaces are provided to enable software to request allocation of a new sparse memory region or allocate sparse memory from an existing sparse memory region. Operations associated with access to sparse memory regions include detecting whether data for read and write request are all zeros.

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