公开(公告)号：US20130275935A1

公开(公告)日：2013-10-17

申请号：US13446418

申请日：2012-04-13

申请人： Mahbub Rashed ,  David Doman ,  Dinesh Somasekhar ,  Yan Wang ,  Yunfei Deng ,  Navneet Jain ,  Jongwook Kye ,  Ali Keshavarzi ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  David Doman ,  Dinesh Somasekhar ,  Yan Wang ,  Yunfei Deng ,  Navneet Jain ,  Jongwook Kye ,  Ali Keshavarzi ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

摘要： An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.

摘要翻译： 公开了一种从平面设计提供定时关闭的FinFET设计的方法。 实施例包括：接收与平面设计相关联的一个或多个平面单元; 基于平面单元和FinFET模型产生对应于平面设计的初始FinFET设计; 并处理初始FinFET设计以提供定时关闭的FinFET设计。 其他实施例包括：基于初始FinFET设计的时序分析确定与初始FinFET设计的路径相关联的竞争条件; 以及与解决与竞争条件相关联的持续违规的路径相关联的增加的延迟，其中初始FinFET设计的处理基于延迟增加。

公开(公告)号：US07872311B2

公开(公告)日：2011-01-18

申请号：US11857122

申请日：2007-09-18

申请人： Marius K. Orlowski ,  Suresh Venkatesan

发明人： Marius K. Orlowski ,  Suresh Venkatesan

IPC分类号： H01L29/76

CPC分类号： H01L29/7846 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78687

摘要： A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axially stress are both compressive for P-channel transistors and tensile for N-channel transistors. Both transistor types can be included on the same integrated circuit.

摘要翻译： 提出了一种在晶体管的沟道区域中提供迁移率增强的方法和装置。 在一个实施例中，沟槽区域（18）形成在双轴向应力的衬底上。 源极（30）和漏极（32）区域形成在衬底上。 源极和漏极区域向双向应力通道区域提供额外的单轴应力。 单向应力和双轴向应力对于P沟道晶体管是压缩的，对于N沟道晶体管是拉伸的。 两种晶体管类型都可以包含在同一集成电路中。

公开(公告)号：US07456055B2

公开(公告)日：2008-11-25

申请号：US11375890

申请日：2006-03-15

申请人： Marius K. Orlowski ,  Suresh Venkatesan

发明人： Marius K. Orlowski ,  Suresh Venkatesan

IPC分类号： H01L21/00

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66795 ,  H01L29/785

摘要： An electronic device can include a base layer, a semiconductor layer, and a first semiconductor fin spaced apart from and overlying a semiconductor layer. In a particular embodiment, a second semiconductor fin can include a portion of the semiconductor layer. In another aspect, a process of forming an electronic device can include providing a workpiece that includes a base layer, a first semiconductor layer that overlies and is spaced apart from a base layer, a second semiconductor layer that overlies, and an insulating layer lying between the first semiconductor layer and the second semiconductor layer. The process can also include removing a portion of the second semiconductor layer to form a first semiconductor fin, and forming a conductive member overlying the first semiconductor fin.

摘要翻译： 电子器件可以包括基极层，半导体层和与半导体层间隔开并覆盖半导体层的第一半导体鳍片。 在特定实施例中，第二半导体鳍片可以包括半导体层的一部分。 另一方面，形成电子器件的工艺可以包括提供一种工件，其包括基底层，覆盖并与基底层间隔开的第一半导体层，覆盖在第二半导体层之间的绝缘层和位于第二半导体层之间的绝缘层 第一半导体层和第二半导体层。 该工艺还可以包括去除第二半导体层的一部分以形成第一半导体鳍片，以及形成覆盖在第一半导体鳍片上的导电构件。

公开(公告)号：US20050275018A1

公开(公告)日：2005-12-15

申请号：US10865351

申请日：2004-06-10

申请人： Suresh Venkatesan ,  Mark Foisy ,  Michael Mendicino ,  Marius Orlowski

发明人： Suresh Venkatesan ,  Mark Foisy ,  Michael Mendicino ,  Marius Orlowski

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203

摘要： A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers, both the N and P channel transistors can be optimized for carrier mobility.

摘要翻译： 半导体器件结构使用两个半导体层来分别优化N沟道晶体管和P沟道晶体管的载流子迁移率。 用于确定的导电特性是半导体的材料类型，晶面，取向和应变的组合。 当导电特性的特征在于半导体材料为硅锗时，p型沟道晶体管的空穴迁移率得到改善，应变为压缩，晶面为（100），取向为100。 或者，晶面可以是（111），在这种情况下的取向是不重要的。 用于N型导电的优选衬底不同于用于P型导电的优选（或最佳）衬底。 N沟道晶体管优选具有拉伸应变，硅半导体材料和（100）平面。 通过分开的半导体层，N沟道晶体管和P沟道晶体管都可以优化载流子迁移率。

公开(公告)号：US06713381B2

公开(公告)日：2004-03-30

申请号：US10051262

申请日：2002-01-18

申请人： Alexander L. Barr ,  Suresh Venkatesan ,  David B. Clegg ,  Rebecca G. Cole ,  Olubunmi Adetutu ,  Stuart E. Greer ,  Brian G. Anthony ,  Ramnath Venkatraman ,  Gregor Braeckelmann ,  Douglas M. Reber ,  Stephen R. Crown

发明人： Alexander L. Barr ,  Suresh Venkatesan ,  David B. Clegg ,  Rebecca G. Cole ,  Olubunmi Adetutu ,  Stuart E. Greer ,  Brian G. Anthony ,  Ramnath Venkatraman ,  Gregor Braeckelmann ,  Douglas M. Reber ,  Stephen R. Crown

IPC分类号： H01L214763

CPC分类号： H01L21/76849 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/54473 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2924/013 ,  H01L2924/0496 ,  H01L2924/0539 ,  H01L2924/0538 ,  H01L2924/0537

摘要： An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

摘要翻译： 互连覆盖半导体器件衬底（10）。 在一个实施例中，导电阻挡层覆盖在互连的一部分上，钝化层（92）覆盖在导电阻挡层上，钝化层（92）具有暴露导电阻挡层（82）的部分的开口。 在替代实施例中，钝化层（22）覆盖互连，钝化层（22）具有暴露互连的开口（24），并且导电阻挡层（32）覆盖开口（24）内的互连。

公开(公告)号：US06551919B2

公开(公告)日：2003-04-22

申请号：US09970284

申请日：2001-10-03

申请人： Suresh Venkatesan ,  Bradley P. Smith ,  Mohammed Rabiul Islam

发明人： Suresh Venkatesan ,  Bradley P. Smith ,  Mohammed Rabiul Islam

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  Y10S438/97

摘要： A dual inlaid copper interconnect structure uses a plasma enhanced nitride (PEN) bottom capping layer and a silicon rich silicon oxynitride intermediate etch stop layer. The interfaces (16a, 16b, 20a, and 20b) between these layers (16 and 20) and their adjacent dielectric layers (18 and 22) are positioned in the stack (13) independent of the desired aspect ratio of trench openings of the copper interconnect in order to improve optical properties of the dielectric stack (13). Etch processing is then used to position the layers (16) and (20) at locations within the inlaid structure depth that result in one or more of reduced DC leakage current, improved optical performance, higher frequency of operation, reduced cross talk, increased flexibility of design, or like improvements.

公开(公告)号：US06444569B1

公开(公告)日：2002-09-03

申请号：US09835276

申请日：2001-04-16

申请人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

发明人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

IPC分类号： H01L214763

摘要： A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

公开(公告)号：US06274478B1

公开(公告)日：2001-08-14

申请号：US09352136

申请日：1999-07-13

申请人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

发明人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/3212

摘要： A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scrubber.

摘要翻译： 铜互连抛光工艺通过使用第一压板抛光（17）铜（63）的体积厚度开始。 然后使用第二压板来去除（19）薄的剩余界面铜层以暴露阻挡膜（61）。 计算机控制（21）监测第一和第二压板的抛光时间并调整这些时间以提高晶片的吞吐量。 一个或多个压板和/或晶片在界面铜抛光剂和阻隔抛光剂之间漂洗（20），以减少淤浆交叉污染。 然后使用第三压板和浆料抛光掉屏障（61）的暴露部分以完成铜互连结构的抛光。 使用含有防腐蚀液体的储存罐将晶片排队，直到后续的擦洗操作（25）。 使用基本上无光的擦洗操作（25）用于减少洗涤器的干燥室中的铜的光伏诱发的腐蚀。

公开(公告)号：US5349228A

公开(公告)日：1994-09-20

申请号：US163322

申请日：1993-12-07

申请人： Gerold W. Neudeck ,  Suresh Venkatesan

发明人： Gerold W. Neudeck ,  Suresh Venkatesan

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/78 ,  H01L27/01 ,  H01L27/13

CPC分类号： H01L29/66772 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78654

摘要： A method for forming a dual-gated Semiconductor-On-Insulator (SOI) field effect transistor for integrated circuits includes the formation of a gate/oxide/channel/oxide/gate stack on top of an insulating layer. The process begins with the formation of a first gate electrode and first oxide layer on an insulating layer. Then, a seed hole in the insulating layer is formed exposing the underlying substrate. This is followed by the epitaxial lateral overgrowth (ELO) of monocrystalline silicon, for example, from the seed hole to on top of the first oxide layer. This monocrystalline layer forms the device channel. A second oxide and second gate electrode layer are then grown and deposited, respectively. Subsequent etch steps employing sidewall spacers are then employed to form a multilayered stack having self-aligned first and second gate electrodes. Sidewall seed holes are then used to epitaxially grow monocrystalline source and drain regions from the channel. In-situ doping can be provided to form a lightly doped source (LDS) and drain (LDD) structure with vertically displaced source and drain contacts.

摘要翻译： 用于形成用于集成电路的双门控半导体绝缘体（SOI）场效应晶体管的方法包括在绝缘层顶部形成栅极/氧化物/沟道/氧化物/栅极堆叠。 该过程开始于在绝缘层上形成第一栅电极和第一氧化物层。 然后，形成绝缘层中的种子孔，暴露下面的衬底。 之后是单晶硅的外延横向过度生长（ELO），例如从第一氧化物层的种子孔到顶部。 该单晶层形成器件沟道。 然后分别生长和沉积第二氧化物和第二栅极电极层。 随后使用采用侧壁间隔物的后续蚀刻步骤形成具有自对准的第一和第二栅电极的多层堆叠。 然后将侧壁孔用于从通道外延生长单晶源极和漏极区域。 可以提供原位掺杂以形成具有垂直移位的源极和漏极触点的轻掺杂源（LDS）和漏极（LDD）结构。