公开(公告)号：US5154514A

公开(公告)日：1992-10-13

申请号：US751490

申请日：1991-08-29

申请人： Jeffrey P. Gambino ,  Louis L. Hsu ,  Michael A. Lee ,  Krishna Seshan ,  Alvin Sugerman ,  Francis E. Turene

发明人： Jeffrey P. Gambino ,  Louis L. Hsu ,  Michael A. Lee ,  Krishna Seshan ,  Alvin Sugerman ,  Francis E. Turene

IPC分类号： G01K7/01

CPC分类号： G01K7/01

摘要： A temperature sensor, comprising: a diode structure including, a) a silicon substrate, b) a first region of a metal silicide in the silicon substrate, c) a second region of a metal-oxide semiconductor material on the first region, d) a third region of a metal over the second region; and, means for using the diode structure as a temperature sensitive device to measure an ambient temperature. The metal-oxide semiconductor material is preferably selected to have a bandgap of not less than about 3.0 eV.

摘要翻译： 1.一种温度传感器，包括：二极管结构，包括：a）硅衬底，b）所述硅衬底中的金属硅化物的第一区域，c）所述第一区域上的金属氧化物半导体材料的第二区域，d） 第二区域上的金属的第三区域; 以及用于使用二极管结构作为温度敏感设备来测量环境温度的装置。 金属氧化物半导体材料优选选择为具有不小于约3.0eV的带隙。

公开(公告)号：US07511370B2

公开(公告)日：2009-03-31

申请号：US11203724

申请日：2005-08-15

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L23/52

CPC分类号： H01L24/02 ,  H01L23/50 ,  H01L23/5286 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/00

摘要： An electrical device includes electrical contact pads, a supply voltage bus and an interconnection circuit. The electrical contact pads receive a supply voltage, and the bus is electrically connected to the electrical contact pads. For each electrical contact pad, the interconnection circuit forms a redundant connection between the bus and the electrical contact pad. The electrical device may include a passivation layer that includes windows to establish electrical contact between the electrical contact pads and the supply voltage bus. This window may be elongated in a path that is generally aligned with the path along which the supply voltage bus extends.

摘要翻译： 电气设备包括电接触焊盘，电源电压总线和互连电路。 电接触焊盘接收电源电压，并且总线电连接到电接触焊盘。 对于每个电接触焊盘，互连电路在总线和电接触焊盘之间形成冗余连接。 电气设备可以包括钝化层，其包括窗口以建立电接触焊盘和电源电压总线之间的电接触。 该窗口可以在通常与电源电压总线延伸的路径对齐的路径中延伸。

公开(公告)号：US20080078994A1

公开(公告)日：2008-04-03

申请号：US11529870

申请日：2006-09-29

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L23/58

CPC分类号： H01L23/585 ,  H01L25/0657 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic die includes: a die substrate; an integrated circuit supported in an active area of the substrate; a plurality of bond pads disposed at a surface of the substrate, at least some of the bond pads being coupled to the integrated circuit; a guard wall supported in the substrate and surrounding a periphery of the active region; and electrical connections adapted to apply a voltage differential across the guard wall to allow a damage testing of the guard wall.

摘要翻译： 微电子管芯包括：芯片基板; 支撑在基板的有源区域中的集成电路; 多个接合焊盘，其设置在所述衬底的表面处，所述接合焊盘中的至少一些耦合到所述集成电路; 保护壁支撑在基板中并且围绕有源区域的周边; 以及适于在保护壁上施加电压差以允许防护墙的损坏测试的电气连接。

公开(公告)号：US07033923B2

公开(公告)日：2006-04-25

申请号：US11056324

申请日：2005-02-10

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L21/44

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00

摘要： The present invention discloses a novel layout and process for a device with segmented BLM for the I/Os. In a first embodiment, each BLM is split into two segments. The segments are close to each other and connected to the same overlying bump. In a second embodiment, each BLM is split into more than two segments. In a third embodiment, each segment is electrically connected to more than one underlying via. In a fourth embodiment, each segment is electrically connected to more than one underlying bond pad.

摘要翻译： 本发明公开了一种用于I / O的具有分段BLM的设备的新颖布局和过程。 在第一实施例中，每个BLM被分成两个段。 这些片段彼此靠近并连接到相同的上覆凸起。 在第二实施例中，每个BLM被分成多于两个段。 在第三实施例中，每个段电连接到多于一个的底层通孔。 在第四实施例中，每个段电连接到多于一个的底层接合焊盘。

公开(公告)号：US20050247931A1

公开(公告)日：2005-11-10

申请号：US11184521

申请日：2005-07-19

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L23/50 ,  H01L23/538 ,  H01L23/58

CPC分类号： G01R31/31718 ,  G01R31/31723 ,  H01L23/50 ,  H01L23/5382 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Selectable capacitors are used to modify performance characteristics of functional circuit elements of an integrated circuit (IC). In an embodiment, the decoupling capacitors are implemented as additional or alternative mounting pads on a surface of the IC. At least one selectable capacitor is provided for each IC circuit element, such as a logic network, whose operational characteristic(s) is predicted to be and is actually identified as sub-optimal through IC testing, particularly following a process change, a mask shrink, operation of the IC at higher clock frequency, or the like. Expensive redesign is avoided by selectively coupling capacitors into the IC circuit element as needed, under control of selector logic that is responsive to control signals. Methods of operation, as well as application of the apparatus to an electronic assembly and an electronic system, are also described.

摘要翻译： 可选择的电容器用于修改集成电路（IC）的功能电路元件的性能特征。 在一个实施例中，去耦电容器被实现为IC表面上的附加或替代的安装焊盘。 为每个IC电路元件（例如逻辑网络）提供至少一个可选择的电容器，其逻辑网络的操作特性被预测为并通过IC测试被实际识别为次优，特别是在过程变化之后，掩模收缩 ，在较高时钟频率下操作IC等。 在根据控制信号响应的选择器逻辑的控制下，通过选择性地将电容器耦合到IC电路元件中来避免昂贵的重新设计。 还描述了操作方法以及将装置应用于电子组件和电子系统。

公开(公告)号：US06876053B1

公开(公告)日：2005-04-05

申请号：US09374502

申请日：1999-08-13

申请人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

发明人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

IPC分类号： H01L21/762 ,  H01L29/00 ,  H01L29/76 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/7846 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

摘要翻译： 一种用于修改MOS器件的隔离结构配置以诱导或减小MOS器件的有源区上的拉伸和/或压缩应力的装置和方法。 根据本发明的隔离结构构造包括使用低模量和高模量介电材料以及拉伸应力诱导和压应力诱导介电材料，还包括改变隔离深度 用于改变隔离结构构造的结构和方法，例如使用的沟槽深度和隔离材料，以修饰（即，诱发或减少）半导体器件的有源区域上的拉伸和/或压缩应力。

公开(公告)号：US06734544B2

公开(公告)日：2004-05-11

申请号：US10387046

申请日：2003-03-12

申请人： Soupin Yan ,  Krishna Seshan

发明人： Soupin Yan ,  Krishna Seshan

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L21/563 ,  H01L24/13 ,  H01L24/81 ,  H01L2223/54473 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14133 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H05K1/0263 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit package is disclosed. According to one embodiment of the present invention an integrated circuit is formed in a die having an edge, and a plurality of non-I/O columns are bonded between a substrate and the die a selected distance from the edge of the die.

摘要翻译： 公开了一种集成电路封装。 根据本发明的一个实施例，在具有边缘的模具中形成集成电路，并且多个非I / O列结合在距离管芯边缘一定距离的衬底和管芯之间。

公开(公告)号：US06646324B1

公开(公告)日：2003-11-11

申请号：US09609434

申请日：2000-06-30

申请人： Sanjay Dabral ,  Krishna Seshan

发明人： Sanjay Dabral ,  Krishna Seshan

IPC分类号： H01L2900

CPC分类号： H01L29/66659 ,  H01L29/7835 ,  Y02P80/30

摘要： A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.

摘要翻译： 描述了用于线性化输出驱动器和终止器的方法和装置。 在一个实施例中，该方法包括在衬底上形成栅电极，衬底的由栅电极覆盖的部分限定沟道。 该方法还包括在衬底的栅电极的横向相对侧上形成第一源极/漏极掺杂区域。 该方法还包括在基板上的栅电极的横向相对侧上形成间隔物。 该方法还包括在与栅电极充分远的第一源极/漏极掺杂区域内的位置处形成线性化的漏极接触区域，以在布置在栅极电极和线性化漏极接触之间的第一源极/漏极掺杂区域中限定串联电阻器 基于源极/漏极掺杂区域的预期电阻率的区域，串联电阻器电连接到沟道。

公开(公告)号：US06377457B1

公开(公告)日：2002-04-23

申请号：US09660859

申请日：2000-09-13

申请人： Krishna Seshan ,  Yves André Volckaert ,  Prosenjit Ghosh

发明人： Krishna Seshan ,  Yves André Volckaert ,  Prosenjit Ghosh

IPC分类号： H05K720

CPC分类号： H05K1/0272 ,  H01L23/467 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic assembly is provided. An electronic substrate of the assembly has a plurality of conductive lines to transmit signals, and a cooling opening therethrough. The cooling opening has an inlet to allow fluid into the electronic substrate, a section in the electronic substrate through which the fluid flows from the inlet, and an outlet from which the fluid flows from the section out of the electronic substrate. A semiconductor die of the assembly is mounted to the electronic substrate. The die has an electronic circuit connected to the metal lines so that signals are transmitted between the electronic circuit and the metal lines, operation of the electronic circuit causing heating of the die, heat being transferred from the die to the electronic substrate from where heat is transferred to the fluid flowing through the section.

摘要翻译： 提供电子组件。 组件的电子基板具有多条传输信号的导线和通过其的冷却开口。 冷却开口具有允许流体进入电子基板的入口，电子基板中的流体从入口流过的部分和流体从该部分流出电子基板的出口。 组件的半导体管芯安装到电子基板上。 模具具有连接到金属线的电子电路，使得信号在电子电路和金属线之间传输，电子电路的操作导致模具的加热，热量从模具转移到电子基板，从那里热量是 转移到流经该部分的流体。

公开(公告)号：US6043551A

公开(公告)日：2000-03-28

申请号：US940535

申请日：1997-09-30

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L23/31 ,  H01L23/58 ,  H01L27/095 ,  H01L31/00

CPC分类号： H01L23/585 ,  H01L23/3171 ,  H01L2924/0002

摘要： An integrated circuit (IC) is provided. The IC includes a silicon substrate and a dielectric layer formed upon the silicon substrate. The IC further includes a terminal metal layer (TML) formed upon the dielectric layer. The dielectric layer and the TML form a die active area. The TML has formed therein a plurality of spaced locking structures. The plurality of space locking structures are electrically isolated therebetween. Each locking structure is formed outside the die active area. The IC further includes a passivation layer adhering to the locking structures.

摘要翻译： 提供集成电路（IC）。 IC包括硅衬底和形成在硅衬底上的电介质层。 IC还包括形成在电介质层上的端子金属层（TML）。 电介质层和TML形成管芯有源区。 TML中形成有多个间隔开的锁定结构。 多个空间锁定结构之间电隔离。 每个锁定结构形成在模具有效区域的外部。 IC还包括粘附到锁定结构的钝化层。