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    MEMORY CELL IMPRINT AVOIDANCE
    41.
    发明申请
    MEMORY CELL IMPRINT AVOIDANCE 审中-公开

    公开(公告)号：US20180366176A1

    公开(公告)日：2018-12-20

    申请号：US16111021

    申请日：2018-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy ,  Kirk Prall ,  Ferdinando Bedeschi

    IPC: G11C11/22 ,  G11C29/52 ,  G06F11/10

    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

    CELL PERFORMANCE RECOVERY USING CYCLING TECHNIQUES
    42.
    发明申请
    CELL PERFORMANCE RECOVERY USING CYCLING TECHNIQUES 审中-公开

    公开(公告)号：US20180358076A1

    公开(公告)日：2018-12-13

    申请号：US16044310

    申请日：2018-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy

    IPC: G11C11/22

    Abstract: Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.

    Memory cell imprint avoidance
    43.
    发明授权
    Memory cell imprint avoidance 有权

    公开(公告)号：US09721639B1

    公开(公告)日：2017-08-01

    申请号：US15188886

    申请日：2016-06-21

    Applicant: Micron Technology, Inc.

    Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy ,  Kirk Prall ,  Ferdinando Bedeschi

    IPC: G11C11/22 ,  G06F11/10 ,  G11C29/52

    CPC classification number: G11C11/2275 ,  G06F11/1048 ,  G06F11/1068 ,  G11C11/221 ,  G11C11/2273 ,  G11C29/52

    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

    Resistive memory sensing
    47.
    发明授权
    Resistive memory sensing 有权
    电阻式记忆感测

    公开(公告)号：US09058875B2

    公开(公告)日：2015-06-16

    申请号：US13921951

    申请日：2013-06-19

    Applicant: Micron Technology, Inc.

    Inventor： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

    Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

    Abstract translation: 本公开包括用于感测电阻式存储单元的装置和方法。 许多实施例包括对存储器单元执行感测操作以确定与存储器单元相关联的当前值，将编程信号施加到存储器单元，以及基于与存储器单元相关联的当前值来确定存储器单元的数据状态 在施加编程信号之前应用编程信号的存储单元和与存储器单元相关联的当前值。

    DIFFERENTIAL STORAGE IN MEMORY ARRAYS
    49.
    发明公开
    DIFFERENTIAL STORAGE IN MEMORY ARRAYS 审中-公开

    公开(公告)号：US20240127877A1

    公开(公告)日：2024-04-18

    申请号：US18047568

    申请日：2022-10-18

    Applicant: Micron Technology, Inc.

    Inventor： Durai Vishak Nirmal Ramaswamy ,  Giorgio Servalli ,  Angelo Visconti ,  Marcello Mariani ,  Alessandro Calderoni

    IPC: G11C11/22 ,  G11C7/06

    CPC classification number: G11C11/2257 ,  G11C7/067 ,  G11C11/2297

    Abstract: Methods, systems, and devices for differential storage in memory arrays are described. A memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). Additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. In one example, the memory device may include pairs of memory cells within a single memory array on a single level. Here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. Additionally, each memory cell pair may include memory cells each coupled with different digit lines.

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