公开(公告)号：US20180337087A1

公开(公告)日：2018-11-22

申请号：US15598795

申请日：2017-05-18

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Scott L. Light ,  John A. Smythe ,  Sony Varghese

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/06 ,  G03F7/075 ,  G03F7/038 ,  G03F7/039 ,  G03F7/20 ,  G03F7/30

CPC classification number: H01L21/76224 ,  G03F7/038 ,  G03F7/039 ,  G03F7/0757 ,  G03F7/20 ,  G03F7/30 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/02345 ,  H01L21/31053 ,  H01L21/31058 ,  H01L29/0649

Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation. Subsequently, the photopatternable dielectric material is developed to pattern the photopatternable dielectric material into a first dielectric structure which at least partially fills the opening, and to remove the photopatternable dielectric material from over the upper surface.

公开(公告)号：US10121662B2

公开(公告)日：2018-11-06

申请号：US15889598

申请日：2018-02-06

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu

IPC: H01L51/40 ,  G01N15/06 ,  G01N33/00 ,  G01N33/48 ,  H01L21/033 ,  B81C1/00 ,  H01L21/308 ,  H01L21/768

Abstract: A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.

公开(公告)号：US20180301539A1

公开(公告)日：2018-10-18

申请号：US16004908

申请日：2018-06-11

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu

IPC: H01L29/49 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/24 ,  H01L27/12 ,  H01L27/105

CPC classification number: H01L29/7869 ,  B82Y10/00 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42392 ,  H01L29/49 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.

公开(公告)号：US10062432B2

公开(公告)日：2018-08-28

申请号：US14719053

申请日：2015-05-21

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

公开(公告)号：US10026889B2

公开(公告)日：2018-07-17

申请号：US15057909

申请日：2016-03-01

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sumeet C. Pandey

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attracter species having at least one trap site and a chemical affinity for the diffusive species. The diffusive species is transferred from the precursor magnetic material to the precursor trap material where it bonds to the at least one attracter species at the trap sites. The species of the enriched trap material may intermix such that the enriched trap material becomes or stays amorphous. The depleted magnetic material may then be crystallized through propagation from a neighboring crystalline material without interference from the amorphous, enriched trap material. This enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.

公开(公告)号：US20180188647A1

公开(公告)日：2018-07-05

申请号：US15908355

申请日：2018-02-28

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade ,  Gurtej S. Sandhu

IPC: G03F7/00 ,  G02B6/00 ,  G03F7/20

CPC classification number: G03F7/0005 ,  G02B6/00 ,  G02B6/136 ,  G03F7/70283

Abstract: A method of forming a photonic device structure comprises forming a photoresist over a photonic material over a substrate. The photoresist is exposed to radiation through a gray-tone mask to form at least one photoexposed region and at least one non-photoexposed region of the photoresist. The at least one photoexposed region of the photoresist or the at least one non-photoexposed region of the photoresist is removed to form photoresist features. The photoresist features and unprotected portions of the photonic material are removed to form photonic features. Other methods of forming a photonic device structure, and a method of forming an electronic device are also described.

公开(公告)号：US09921471B2

公开(公告)日：2018-03-20

申请号：US14495278

申请日：2014-09-24

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade ,  Gurtej S. Sandhu

IPC: G03F7/00 ,  G03F7/20 ,  G02B6/00

CPC classification number: G03F7/0005 ,  G02B6/00 ,  G03F7/70283

Abstract: A method of forming a photonic device structure comprises forming a photoresist over a photonic material over a substrate. The photoresist is exposed to radiation through a gray-tone mask to form at least one photoexposed region and at least one non-photoexposed region of the photoresist. The at least one photoexposed region of the photoresist or the at least one non-photoexposed region of the photoresist is removed to form photoresist features. The photoresist features and unprotected portions of the photonic material are removed to form photonic features. Other methods of forming a photonic device structure, and a method of forming an electronic device are also described.

公开(公告)号：US20180061635A1

公开(公告)日：2018-03-01

申请号：US15798672

申请日：2017-10-31

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu

IPC: H01L21/02 ,  H01L29/02 ,  H01L21/311 ,  H01L21/033

Abstract: A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. Each of the regions on the patterned substrate is specifically tailored for adsorption of specific nucleic acid structure in the directed self-assembly.

公开(公告)号：US09881786B2

公开(公告)日：2018-01-30

申请号：US14677445

申请日：2015-04-02

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu

IPC: H01L21/02 ,  H01L21/311 ,  H01L29/02 ,  H01L21/033

CPC classification number: H01L21/02118 ,  B82Y40/00 ,  H01L21/02227 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31138 ,  H01L29/02 ,  H01L29/0665 ,  H01L29/66007

Abstract: A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. Each of the regions on the patterned substrate is specifically tailored for adsorption of specific nucleic acid structure in the directed self-assembly.

公开(公告)号：US09805789B2

公开(公告)日：2017-10-31

申请号：US14308786

申请日：2014-06-19

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

IPC: H01L29/22 ,  H01L21/36 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0007 ,  G11C2213/55 ,  G11C2213/56 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616

Abstract: Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode.