公开(公告)号：US20150014811A1

公开(公告)日：2015-01-15

申请号：US14499720

申请日：2014-09-29

Applicant: Micron Technology, Inc.

Inventor： Casey Smith ,  Jasper S. Gibbons ,  Kunal R. Parekh

IPC: H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5252 ,  H01L21/76879 ,  H01L21/823425 ,  H01L21/82345 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Antifuses having two or more materials with differing work function values may be fabricated as recessed access devices and spherical recessed access devices for use with integrated circuit devices and semiconductor devices. The use of materials having different work function values in the fabrication of recessed access device antifuses allows the breakdown areas of the antifuse device to be customized or predicted.

Abstract translation: 具有两种或更多种具有不同功函数值的材料的防潮剂可以被制造为用于集成电路器件和半导体器件的凹陷入口器件和球形凹入入口器件。 在制造嵌入式接入装置反熔丝中使用具有不同功函数的材料允许定制或预测反熔丝装置的击穿面积。

公开(公告)号：US20140287584A1

公开(公告)日：2014-09-25

申请号：US14144806

申请日：2013-12-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Philip J. Ireland ,  Sarah A. Niroumand

IPC: H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/02063 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2224/13025 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.

Abstract translation: 具有通硅通孔的微电子器件及其相关制造方法。 一种用于形成钨硅通孔的方法的一个实施例，包括形成具有侧壁的开口，使得所述开口延伸穿过已经形成有微电子结构的衬底的至少一部分。 该方法可以进一步包括用介电材料衬里侧壁，在介电材料上沉积钨，使得空腔延伸穿过钨的至少一部分，并用多晶硅材料填充空腔。

公开(公告)号：US20250142827A1

公开(公告)日：2025-05-01

申请号：US19009758

申请日：2025-01-03

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H10B43/27 ,  H10D30/01 ,  H10D30/63 ,  H10D48/36

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US20250142820A1

公开(公告)日：2025-05-01

申请号：US19009060

申请日：2025-01-03

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20250104761A1

公开(公告)日：2025-03-27

申请号：US18971871

申请日：2024-12-06

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Glen E. Hush ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

公开(公告)号：US20240422993A1

公开(公告)日：2024-12-19

申请号：US18815624

申请日：2024-08-26

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H10B63/00 ,  G11C5/06 ,  H01L25/16 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10N70/00

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a first control logic region comprising first control logic devices, and a first memory array region vertically overlying the first control logic region and comprising an array of vertically extending strings of memory cells. An additional microelectronic device structure comprising a semiconductive material is attached to an upper surface of the microelectronic device structure. A portion of the semiconductive material is removed. A second control logic region is formed over the first memory array region. The second control logic region comprises second control logic devices and a remaining portion of the semiconductive material. A second memory array region is formed over the second control logic region. The second memory array region comprises an array of resistance variable memory cells. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US12165696B2

公开(公告)日：2024-12-10

申请号：US17830981

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Glen E. Hush ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

公开(公告)号：US20240381631A1

公开(公告)日：2024-11-14

申请号：US18783273

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Surendranath C. Eruvuru

IPC: H10B41/27 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H10B43/27

Abstract: An electronic device includes one or more capacitors adjacent to a base material. The one or more capacitors comprise at least one electrode extending horizontally within the base material, and additional electrodes extending vertically within the base material and contacting the at least one electrode. The at least one electrode is located below and isolated from an upper surface of the base material. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20240334717A1

公开(公告)日：2024-10-03

申请号：US18424713

申请日：2024-01-26

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Russell L. Meyer

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A method of forming a microelectronic device includes forming a first assembly including a semiconductor base structure, a first circuitry region including first devices at a first boundary of the semiconductor base structure, and a second circuitry region including second devices at a second boundary of the semiconductor base structure vertically offset from the first boundary. A microelectronic device structure is formed and includes a stack structure including tiers individually including conductive material and insulative material vertically adjacent the conductive material, and cell pillar structures including semiconductor material vertically extending through the stack structure. The first assembly is attached to the microelectronic device structure to form a second assembly. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240313098A1

公开(公告)日：2024-09-19

申请号：US18598735

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: H01L29/775 ,  H01L23/00 ,  H01L25/065 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L29/775 ,  H01L24/80 ,  H01L25/0657 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696 ,  H01L2224/80895 ,  H01L2924/1436 ,  H10B12/01

Abstract: Methods, systems, and devices for transistor architectures in coupled semiconductor systems are described. A memory system may be formed from multiple semiconductor components (e.g., multiple dies, multiple wafers) that are coupled together, with different semiconductor components implementing different techniques for transistor formation. For example, a first die may include a memory array and first circuitry configured to access the memory array, and a second die coupled with the first die may include second circuitry configured to access the memory array. The first circuitry may include transistors formed in accordance with a first fabrication technique (e.g., to form a first type of transistors) and the second circuitry may include transistors formed in accordance with a second fabrication technique (e.g., to form a second type of transistors). The dies may be coupled in a manner that provides an electrical coupling between the first circuitry and the second circuitry.