公开(公告)号：US20240222145A1

公开(公告)日：2024-07-04

申请号：US18602553

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Jonathan S. Hacker

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3157 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/91 ,  H01L24/83 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/26145 ,  H01L2224/29023 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83007 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/18161

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

公开(公告)号：US20210118852A1

公开(公告)日：2021-04-22

申请号：US16939756

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/66 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01Q1/48 ,  H01Q1/22

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US20200350224A1

公开(公告)日：2020-11-05

申请号：US16936639

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L25/00 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18 ,  H01L23/373 ,  H01L23/42

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US20200083178A1

公开(公告)日：2020-03-12

申请号：US16127769

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Bret K. Street ,  Wei Zhou ,  Christopher J. Gambee ,  Jonathan S. Hacker ,  Shijian Luo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

公开(公告)号：US20200075384A1

公开(公告)日：2020-03-05

申请号：US16119414

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Owen R. Fay

IPC: H01L21/683

Abstract: A semiconductor device assembly that includes a semiconductor device having a first side and a second side connected to a substrate. A layer of self-depolymerizing polymer connects the semiconductor device to the substrate. The layer of self-depolymerizing layer is positioned between the first side of the semiconductor device and the substrate. The layer of self-depolymerizing polymer is configured to selectively release the substrate from the semiconductor device. The layer of self-depolymerizing polymer selectively depolymerizes to release the substrate. The substrate enables processing to occur on the second side of the semiconductor device. A material may be applied to a portion of the layer of self-depolymerizing polymer causing the entire layer to depolymerize and release the substrate from the semiconductor device. Energy may be applied to a portion of the layer of self-depolymerizing polymer causing the entire layer to depolymerize and release the substrate from the semiconductor device.

公开(公告)号：US10134655B2

公开(公告)日：2018-11-20

申请号：US15874406

申请日：2018-01-18

Applicant: Micron Technology, Inc.

Inventor： Steven Groothuis ,  Jian Li ,  Shijian Luo

IPC: H01L21/00 ,  H01L23/02 ,  H01L23/367 ,  H01L25/065 ,  H01L23/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48

Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate.

公开(公告)号：US10103134B2

公开(公告)日：2018-10-16

申请号：US15728123

申请日：2017-10-09

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma ,  Sony Varghese ,  Jonathan S. Hacker ,  Bret K. Street ,  Shijian Luo

IPC: H01L29/40 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78 ,  H01L23/544

Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.

公开(公告)号：US09899293B2

公开(公告)日：2018-02-20

申请号：US15401762

申请日：2017-01-09

Applicant: Micron Technology, Inc.

Inventor： Steven Groothuis ,  Jian Li ,  Shijian Luo

IPC: H01L21/00 ,  H01L21/44 ,  H01L23/367 ,  H01L25/065 ,  H01L21/56 ,  H01L23/48 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/18161 ,  H01L2924/00

Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate. A heat sink may be located on a side of the uppermost semiconductor die opposite the substrate. A passivation material may be located between the uppermost semiconductor die and the heat sink.

公开(公告)号：US09543274B2

公开(公告)日：2017-01-10

申请号：US14605466

申请日：2015-01-26

Applicant: Micron Technology, Inc.

Inventor： Steven Groothuis ,  Jian Li ,  Shijian Luo

IPC: H01L21/00 ,  H01L23/02 ,  H01L25/065 ,  H01L23/48 ,  H01L21/56 ,  H01L23/13

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/18161 ,  H01L2924/00

Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. The stack of semiconductor dice may include vias extending through each semiconductor die of the stack for electrically interconnecting the semiconductor dice in the stack to one another and to the substrate. Another semiconductor die may be electrically connected to the stack of semiconductor dice and may be located on a side of the stack of semiconductor dice opposing the substrate. The other semiconductor die may be a heat-generating component configured to generate more heat than each semiconductor die of the stack of semiconductor dice. Electrical connectors may be located laterally adjacent to the vias and may form electrical connections between the substrate and the other semiconductor die in isolation from integrated circuitry of the semiconductor dice in the stack.

Abstract translation: 根据本公开的半导体器件封装可以包括衬底和附接到衬底的半导体管芯堆叠。 半导体晶片的堆叠可以包括延伸穿过堆叠的每个半导体管芯的通孔，用于将堆叠中的半导体管芯彼此彼此和衬底电互连。 另一个半导体管芯可以电连接到半导体管芯的堆叠，并且可以位于与衬底相对的半导体管芯堆叠的一侧。 另一个半导体管芯可以是被配置成比半导体管芯堆叠的每个半导体管芯产生更多的热量的发热部件。 电连接器可以位于横向邻近通孔的位置，并且可以在堆叠中的半导体裸片的集成电路之外形成衬底和另一半导体管芯之间的电连接。

公开(公告)号：US09157014B2

公开(公告)日：2015-10-13

申请号：US13689144

申请日：2012-11-29

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Xiao Li

IPC: C09J11/04 ,  H01L21/683 ,  C08K3/00 ,  C08K3/04 ,  C08K3/14 ,  C08K3/22 ,  C08K3/36 ,  C08K7/18

CPC classification number: C09J11/04 ,  C08K3/013 ,  C08K3/04 ,  C08K3/14 ,  C08K3/22 ,  C08K3/36 ,  C08K7/18 ,  C09J2203/326 ,  H01L21/6835 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Temporary adhesives include a thermoplastic polymer comprising from about 30% by weight to about 80% by weight of the temporary adhesive, a solvent comprising from about 20% by weight to about 70% by weight of the temporary adhesive, and a filler material comprising from about 0.2% to about 5% by weight of the temporary adhesive. Methods of processing a semiconductor device wafer include bonding the semiconductor device wafer to a surface of a carrier substrate using a temporary adhesive including a filler material comprising from about 0.2% to about 5% by weight of the temporary adhesive, thinning the semiconductor device wafer, and, while the temporary adhesive remains on the surface of the carrier substrate proximate a peripheral edge thereof, subjecting the thinned semiconductor device wafer to one or more back side processing operations. Methods of forming a thinned semiconductor wafer include using such a temporary adhesive.

Abstract translation: 临时粘合剂包括热塑性聚合物，其包含约30重量％至约80重量％的临时粘合剂，包含约20重量％至约70重量％的临时粘合剂的溶剂，以及填料， 约0.2％至约5％的临时粘合剂。 处理半导体器件晶片的方法包括使用包括约0.2重量％至约5重量％的临时粘合剂的填充材料的临时粘合剂将半导体器件晶片接合到载体衬底的表面，使半导体器件晶片变薄， 并且当临时粘合剂在其周边附近残留在载体基板的表面上时，对减薄的半导体器件晶片进行一个或多个背面处理操作。 形成薄化半导体晶片的方法包括使用这种临时粘合剂。