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    Dynamic program window determination in a memory device
    41.
    发明授权
    Dynamic program window determination in a memory device 有权
    在存储设备中动态程序窗口确定

    公开(公告)号：US09455043B2

    公开(公告)日：2016-09-27

    申请号：US15075768

    申请日：2016-03-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tommaso Vali ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

    IPC: G11C11/34 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26

    CPC classification number: G11C16/3436 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3422

    Abstract: A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. The controller is configured to cause the memory device to apply a programming pulse to control gates of the group of memory cells. The controller is configured to determine an amount of disturb experienced by the group of memory cells responsive to the programming pulse. The controller is configured to determine a program window responsive to the amount of disturb.

    Abstract translation: 存储器件具有控制器。 控制器被配置为使得存储器件禁止对一组存储器单元进行编程。 控制器被配置为使存储器件施加编程脉冲来控制该组存储器单元的栅极。 控制器被配置为确定响应于编程脉冲的存储器单元组经历的干扰量。 控制器被配置为响应于干扰量来确定程序窗口。

    Memory cell coupling compensation
    43.
    发明授权
    Memory cell coupling compensation 有权
    存储单元耦合补偿

    公开(公告)号：US09318220B2

    公开(公告)日：2016-04-19

    申请号：US14182032

    申请日：2014-02-17

    Applicant: Micron Technology, Inc.

    Inventor： Zhenlei Shen ,  William H. Radke ,  Peter Feeley

    IPC: G11C16/34 ,  G11C29/04 ,  G11C16/04 ,  G06F11/10 ,  G11C16/06

    CPC classification number: G06F11/1068 ,  G06F11/1004 ,  G06F11/1048 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/04 ,  G11C29/52

    Abstract: Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.

    Abstract translation: 描述了用于存储器单元耦合补偿的方法和被配置为执行其的装置。 用于存储单元耦合补偿的一种或多种方法包括使用根据第一存储单元耦合补偿电压而改变的电压来确定存储单元的状态，对存储单元的状态执行错误检查，以及确定状态 使用响应于错误检查失败的根据第二存储器单元耦合补偿电压而改变的电压的存储器单元。

    STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION
    47.
    发明申请
    STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION 有权
    在具有连接配置中的设备的系统中的状态更改

    公开(公告)号：US20150301746A1

    公开(公告)日：2015-10-22

    申请号：US14755555

    申请日：2015-06-30

    Applicant: Micron Technology, Inc.

    Inventor： William H. Radke ,  Victor Y. Tsai ,  James Cooke ,  Neal A. Galbo ,  Peter Feeley

    IPC: G06F3/06

    CPC classification number: G06F13/102 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/1684 ,  G06F13/4282 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  Y02D10/14 ,  Y02D10/151

    Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

    Abstract translation: 本公开包括用于在具有以链式配置耦合的设备的系统中的状态改变的方法，设备和系统。 许多实施例包括以链式配置耦合到主机的主机和多个设备。 链接配置包括至少一个不直接耦合到主机的设备。 不直接耦合到主机的至少一个设备被配置为响应于从主机接收到命令而从第一通信状态改变到第二通信状态。

    Fault-tolerant non-volatile integrated circuit memory
    48.
    发明授权
    Fault-tolerant non-volatile integrated circuit memory 有权
    容错非易失性集成电路存储器

    公开(公告)号：US09152546B2

    公开(公告)日：2015-10-06

    申请号：US14275599

    申请日：2014-05-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William H. Radke

    IPC: G06F12/00 ,  G06F12/02 ,  G06F11/10 ,  G11C29/00

    CPC classification number: G06F12/0223 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/2022 ,  G06F2212/7208 ,  G11C29/765

    Abstract: Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices.

    Abstract translation: 公开了诸如将数据存储在诸如NAND闪存的多个非易失性集成电路存储器件中的卷积编码的装置和方法。 卷积码的相对较高的码率消耗相对较小的额外的存储空间。 在一个实施例中，卷积码扩展到多个存储器件的部分上，而不是集中在特定存储器件的页面内。 在一个实施例中，使用m / n的码率，并且卷积码被存储在n个存储器装置中。

    Error recovery storage along a memory string
    50.
    发明授权
    Error recovery storage along a memory string 有权
    沿着内存字符串的恢复存储器出错

    公开(公告)号：US09063875B2

    公开(公告)日：2015-06-23

    申请号：US14263825

    申请日：2014-04-28

    Applicant: Micron Technology, Inc.

    Inventor： William H. Radke

    IPC: G06F11/10 ,  H03M13/25 ,  H03M13/29

    CPC classification number: G06F11/1008 ,  G06F11/1072 ,  H03M13/256 ,  H03M13/2909

    Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

    Abstract translation: 设备和方法存储存储器阵列的不同维度的错误恢复数据。 例如，在一个维度中，使用块纠错码（ECC），并且在另一维度中，使用补码纠错码，例如卷积码。 通过使用单独的维度，缺陷影响两种错误恢复技术的可能性减弱，从而增加了可以成功执行错误恢复的概率。 在一个示例中，块错误校正码用于沿着行存储的数据，并且该数据被存储在阵列的多级单元中。 补充纠错码用于沿列存储的数据，例如沿着字符串的单元格，并且补充纠错码存储在与纠错码不同的电平上。

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