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公开(公告)号：US10663859B2
公开(公告)日：2020-05-26
申请号：US15908355
申请日：2018-02-28
Applicant: Micron Technology, Inc.
Inventor： Roy E. Meade , Gurtej S. Sandhu
Abstract: A method of forming a photonic device structure comprises forming a photoresist over a photonic material over a substrate. The photoresist is exposed to radiation through a gray-tone mask to form at least one photoexposed region and at least one non-photoexposed region of the photoresist. The at least one photoexposed region of the photoresist or the at least one non-photoexposed region of the photoresist is removed to form photoresist features. The photoresist features and unprotected portions of the photonic material are removed to form photonic features. Other methods of forming a photonic device structure, and a method of forming an electronic device are also described.
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42.发明授权公开(公告)号：US09991122B2
公开(公告)日：2018-06-05
申请号：US15253454
申请日：2016-08-31
Applicant: Micron Technology, Inc.
Inventor： Roy E. Meade , Sumeet C. Pandey
IPC: H01L21/26 , H01L21/268 , H01L21/477 , H01L29/06 , H01L21/02
CPC classification number: H01L21/268 , H01L21/02521 , H01L21/02568 , H01L21/0259 , H01L21/02675 , H01L21/428 , H01L21/477 , H01L29/0665
Abstract: A method of forming a semiconductor device structure comprises forming at least one 2D material over a substrate. The at least one 2D material is treated with at least one laser beam having a frequency of electromagnetic radiation corresponding to a resonant frequency of crystalline defects within the at least one 2D material to selectively energize and remove the crystalline defects from the at least one 2D material. Additional methods of forming a semiconductor device structure, and related semiconductor device structures, semiconductor devices, and electronic systems are also described.
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公开(公告)号：US09830970B2
公开(公告)日：2017-11-28
申请号：US15237434
申请日：2016-08-15
Applicant: Micron Technology, Inc.
Inventor： Roy E. Meade
CPC classification number: G11C11/24 , G11C8/08 , G11C11/34 , G11C11/56 , G11C11/565 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0061 , G11C13/0069 , H01L27/101 , H01L28/40 , H01L45/08 , H01L45/12 , H01L45/1233
Abstract: Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.
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44.发明授权Resistive memory cells with two discrete layers of programmable material, methods of programming memory cells, and methods of forming memory cells 有权具有可编程材料的两个离散层的电阻式存储单元，存储单元的编程方法以及形成存储单元的方法公开(公告)号：US09406878B2
公开(公告)日：2016-08-02
申请号：US14444795
申请日：2014-07-28
Applicant: Micron Technology, Inc.
Inventor： Roy E. Meade , Bhaskar Srinivasan , Gurtej S. Sandhu
CPC classification number: H01L45/085 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2213/56 , H01L45/04 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146
Abstract: Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer.
Abstract translation: 一些实施例包括编程存储器单元的方法。 多个电荷载体可以在存储器单元内移动，其中跨越移动电荷载流子的绝对值大于2的平均电荷。一些实施例包括形成和编程基于离子传输的存储单元的方法。 堆叠形成为在第一和第二电极之间具有可编程材料。 可编程材料具有在可编程材料内移动的移动离子，以将可编程材料从一个存储器状态转换到另一个。 移动移动离子上的平均电荷具有大于2的绝对值。一些实施例包括在第一和第二电极之间具有可编程材料的存储单元。 可编程材料包括氮化铝第一层，并且包括含有与第一层共同的可移动离子物质的第二层。
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公开(公告)号：US20160163963A1
公开(公告)日：2016-06-09
申请号：US15045865
申请日：2016-02-17
Applicant: Micron Technology, Inc.
Inventor： Roy E. Meade , Sumeet C. Pandey , Gurtej S. Sandhu
CPC classification number: H01L43/02 , H01L27/222 , H01L43/08 , H01L43/10 , H01L43/12
Abstract: A magnetic cell includes a magnetic tunnel junction that comprises magnetic and nonmagnetic materials exhibiting hexagonal crystal structures. The hexagonal crystal structure is enabled by a seed material, proximate to the magnetic tunnel junction, that exhibits a hexagonal crystal structure matching the hexagonal crystal structure of the adjoining magnetic material of the magnetic tunnel junction. In some embodiments, the seed material is formed adjacent to an amorphous foundation material that enables the seed material to be formed at the hexagonal crystal structure. In some embodiments, the magnetic cell includes hexagonal cobalt (h-Co) free and fixed regions and a hexagonal boron nitride (h-BN) tunnel barrier region with a hexagonal zinc (h-Zn) seed region adjacent the h-Co. The structure of the magnetic cell enables high tunnel magnetoresistance, high magnetic anisotropy strength, and low damping. Methods of fabrication and semiconductor devices are also disclosed.
Abstract translation: 磁性电池包括磁性隧道结，其包括具有六方晶系结构的磁性和非磁性材料。 六方晶体结构通过靠近磁性隧道结的种子材料实现，其表现出与磁性隧道结相邻的磁性材料的六方晶体结构相匹配的六方晶系结构。 在一些实施方案中，种子材料邻近无定形基底材料形成，使得种子材料能够以六方晶体结构形成。 在一些实施方案中，磁性电池包括六方钴（h-Co）游离和固定区域以及与h-Co相邻的六方锌（h-Zn）种子区域的六方氮化硼（h-BN）隧道势垒区。 磁性单元的结构能够实现高隧道磁阻，高磁各向异性强度和低阻尼。 还公开了制造方法和半导体器件。
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Patent Agency Ranking
公开(公告)号：US20150303372A1
公开(公告)日：2015-10-22
申请号：US14256655
申请日：2014-04-18
Applicant: Micron Technology, Inc.
Inventor： Roy E. Meade , Sumeet C. Pandey , Gurtej S. Sandhu
CPC classification number: H01L43/02 , H01L27/222 , H01L43/08 , H01L43/10 , H01L43/12
Abstract: A magnetic cell includes a magnetic tunnel junction that comprises magnetic and nonmagnetic materials exhibiting hexagonal crystal structures. The hexagonal crystal structure is enabled by a seed material, proximate to the magnetic tunnel junction, that exhibits a hexagonal crystal structure matching the hexagonal crystal structure of the adjoining magnetic material of the magnetic tunnel junction. In some embodiments, the seed material is formed adjacent to an amorphous foundation material that enables the seed material to be formed at the hexagonal crystal structure. In some embodiments, the magnetic cell includes hexagonal cobalt (h-Co) free and fixed regions and a hexagonal boron nitride (h-BN) tunnel barrier region with a hexagonal zinc (h-Zn) seed region adjacent the h-Co. The structure of the magnetic cell enables high tunnel magnetoresistance, high magnetic anisotropy strength, and low damping. Methods of fabrication and semiconductor devices are also disclosed.
Abstract translation: 磁性电池包括磁性隧道结，其包括具有六方晶系结构的磁性和非磁性材料。 六方晶体结构通过靠近磁性隧道结的种子材料实现，其表现出与磁性隧道结相邻的磁性材料的六方晶系结构相匹配的六方晶系结构。 在一些实施方案中，种子材料邻近无定形基底材料形成，使得种子材料能够以六方晶体结构形成。 在一些实施方案中，磁性电池包括六方钴（h-Co）游离和固定区域以及与h-Co相邻的六方锌（h-Zn）种子区域的六方氮化硼（h-BN）隧道势垒区。 磁性单元的结构能够实现高隧道磁阻，高磁各向异性强度和低阻尼。 还公开了制造方法和半导体器件。
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47.发明申请Cross-Point Memory Cells, Non-Volatile Memory Arrays, Methods of Reading a Memory Cell, Methods of Programming a Memory Cell, Methods of Writing to and Reading from a Memory Cell, and Computer Systems 有权交叉点存储器单元，非易失性存储器阵列，读取存储器单元的方法，编程存储器单元的方法，写入和读取存储器单元的方法以及计算机系统公开(公告)号：US20150085565A1
公开(公告)日：2015-03-26
申请号：US14557306
申请日：2014-12-01
Applicant: Micron Technology, Inc.
Inventor： Roy E. Meade
CPC classification number: G11C11/24 , G11C8/08 , G11C11/34 , G11C11/56 , G11C11/565 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0061 , G11C13/0069 , H01L27/101 , H01L28/40 , H01L45/08 , H01L45/12 , H01L45/1233
Abstract: Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.
Abstract translation: 描述了交叉点存储器单元，非易失性存储器阵列，读取存储器单元的方法，编程存储器单元的方法，以及写入存储器单元和从存储器单元读取的方法。 在一个实施例中，交叉点存储单元包括在第一方向上延伸的字线，在与第一方向不同的第二方向上延伸的位线，位线和字线交叉而不物理接触， 电容之间形成了字线与位线之间的交叉。 电容器包括被配置为防止直流电流从字线流到位线和从位线到字线的电介质材料。
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48.发明申请SEMICONDUCTOR GRAPHENE STRUCTURES, METHODS OF FORMING SUCH STRUCTURES AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES 有权半导体石墨结构，形成这种结构的方法和包括这种结构的半导体器件公开(公告)号：US20150034908A1
公开(公告)日：2015-02-05
申请号：US14521088
申请日：2014-10-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Roy E. Meade , Sumeet C. Pandey
IPC: H01L29/16 , H01L21/02 , H01L27/092 , H01L29/165 , H01L29/78
CPC classification number: H01L29/1606 , H01L21/02175 , H01L21/02527 , H01L21/02664 , H01L27/092 , H01L29/165 , H01L29/42364 , H01L29/513 , H01L29/517 , H01L29/66045 , H01L29/778 , H01L29/7781 , H01L29/78 , Y02E10/50
Abstract: A semiconducting graphene structure may include a graphene material and a graphene-lattice matching material over at least a portion of the graphene material, wherein the graphene-lattice matching material has a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material. The semiconducting graphene structure may have an energy band gap of at least about 0.5 eV. A method of modifying an energy band gap of a graphene material may include forming a graphene-lattice matching material over at least a portion of a graphene material, the graphene-lattice matching material having a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material.
Abstract translation: 半导体石墨烯结构可以包括在石墨烯材料的至少一部分上的石墨烯材料和石墨烯 - 晶格匹配材料，其中所述石墨烯 - 晶格匹配材料具有在晶格常数的倍数的约±5％内的晶格常数，或 石墨烯材料的粘结长度。 半导体石墨烯结构可以具有至少约0.5eV的能带隙。 修饰石墨烯材料的能带隙的方法可包括在石墨烯材料的至少一部分上形成石墨烯 - 晶格匹配材料，所述石墨烯 - 晶格匹配材料的晶格常数在约±5％ 石墨烯材料的晶格常数或键长度。
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49.发明授权Semiconducting graphene structures, methods of forming such structures and semiconductor devices including such structures 有权半导体石墨烯结构，形成这种结构的方法和包括这种结构的半导体器件公开(公告)号：US08901666B1
公开(公告)日：2014-12-02
申请号：US13954017
申请日：2013-07-30
Applicant: Micron Technology, Inc.
Inventor： Roy E. Meade , Sumeet C. Pandey
IPC: H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L21/02 , H01L29/16
CPC classification number: H01L29/1606 , H01L21/02175 , H01L21/02527 , H01L21/02664 , H01L27/092 , H01L29/165 , H01L29/42364 , H01L29/513 , H01L29/517 , H01L29/66045 , H01L29/778 , H01L29/7781 , H01L29/78 , Y02E10/50
Abstract: A semiconducting graphene structure may include a graphene material and a graphene-lattice matching material over at least a portion of the graphene material, wherein the graphene-lattice matching material has a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material. The semiconducting graphene structure may have an energy band gap of at least about 0.5 eV. A method of modifying an energy band gap of a graphene material may include forming a graphene-lattice matching material over at least a portion of a graphene material, the graphene-lattice matching material having a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material.
Abstract translation: 半导体石墨烯结构可以包括在石墨烯材料的至少一部分上的石墨烯材料和石墨烯 - 晶格匹配材料，其中所述石墨烯 - 晶格匹配材料具有在晶格常数的倍数的约±5％内的晶格常数，或 石墨烯材料的粘结长度。 半导体石墨烯结构可以具有至少约0.5eV的能带隙。 修饰石墨烯材料的能带隙的方法可包括在石墨烯材料的至少一部分上形成石墨烯 - 晶格匹配材料，所述石墨烯 - 晶格匹配材料的晶格常数在约±5％ 石墨烯材料的晶格常数或键长度。
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50.发明申请ELECTRONIC DEVICES INCLUDING TWO OR MORE SUBSTRATES ELECTRICALLY CONNECTED TOGETHER AND METHODS OF FORMING SUCH ELECTRONIC DEVICES 有权包括两个或更多个电子连接的基板的电子器件和形成这样的电子器件的方法公开(公告)号：US20140340861A1
公开(公告)日：2014-11-20
申请号：US14454550
申请日：2014-08-07
Applicant: Micron Technology, Inc.
Inventor： Roy E. Meade , Gurtej S. Sandhu
CPC classification number: H05K1/0298 , B82Y99/00 , G11C8/08 , G11C8/10 , G11C11/14 , G11C11/15 , G11C11/16 , G11C11/161 , G11C19/0808 , H01L24/02 , H01L24/80 , H01L2224/04042 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01093 , H01L2924/014 , H01L2924/12042 , H05K1/112 , H05K1/113 , H05K1/144 , H05K3/3436 , H05K3/36 , H05K3/4697 , H05K7/04 , H05K2201/09381 , Y10S977/932 , Y10T29/49126 , Y10T29/49128 , H01L2924/00
Abstract: Electronic devices may include a first substrate including circuitry components within the substrate, a microscale bond pad on a surface of the substrate, and a via electrically connecting the microscale bond pad to one of the circuitry components. A distance between centers of at least some adjacent circuitry components of the circuitry components may be a nanoscale distance. A second substrate may be electrically connected to the microscale bond pad. Methods of forming electronic devices may involve positioning a first substrate adjacent to a second substrate and electrically connecting the second substrate to a microscale bond pad on a surface of the first substrate. The first substrate may include circuitry components within the first substrate and a via electrically connecting the microscale bond pad to one of the circuitry components. A distance between centers of at least some adjacent circuitry components of the circuitry components may be a nanoscale distance.
Abstract translation: 电子器件可以包括第一衬底，其包括衬底内的电路元件，衬底表面上的微结构焊盘，以及将微结构焊盘电连接到电路部件之一的通孔。 电路部件的至少一些相邻电路部件的中心之间的距离可以是纳米级距离。 第二衬底可以电连接到微结构焊盘。 形成电子器件的方法可以包括将第一衬底定位成与第二衬底相邻并且将第二衬底电连接到第一衬底的表面上的微结构焊盘。 第一衬底可以包括第一衬底内的电路部件和将微结构焊盘电连接到电路部件之一的通孔。 电路部件的至少一些相邻电路部件的中心之间的距离可以是纳米级距离。
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