公开(公告)号：US08211743B2

公开(公告)日：2012-07-03

申请号：US12114096

申请日：2008-05-02

申请人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L21/00

CPC分类号： H01L45/04 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material. The forming thereof includes etching through the conductive material to form opposing laterally outermost conductive edges of said conductive material in the one planar cross section at the conclusion of said etching which are received laterally outward of the opposing laterally outermost edges of the first conductive electrode in the one planar cross section.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 第一导电电极在一个平面横截面中具有垂直最外表面和在最外表面处的相对的横向最外边缘。 在第一导电电极上形成包含多电阻态金属氧化物的材料。 导电材料沉积在多电阻状态的含金属氧化物的材料上。 包含导电材料的存储单元的第二导电电极被接收在多电阻状态的含金属氧化物的材料上。 其形成包括通过导电材料的蚀刻，以在所述蚀刻结束时在一个平面截面中形成所述导电材料的相对的横向最外面的导电边缘，其在第一导电电极的相对的横向最外边缘的横向外侧接收 一个平面截面。

公开(公告)号：US08114468B2

公开(公告)日：2012-02-14

申请号：US12141559

申请日：2008-06-18

申请人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

发明人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

IPC分类号： B05D5/12 ,  B28B19/00 ,  B29B15/00 ,  C23C18/00 ,  C23C20/00 ,  C23C24/00 ,  C23C26/00 ,  C23C28/00 ,  C23C30/00 ,  H01C17/06 ,  H05K3/00 ,  H01L47/00 ,  H01L29/08 ,  H01L35/24 ,  H01L51/00 ,  H01L29/02 ,  H01L21/00 ,  H01L21/16 ,  H01L21/20 ,  H01L21/36 ,  G11C11/00

CPC分类号： H01L27/101 ,  H01L21/0271 ,  Y10S438/947

摘要： A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

摘要翻译： 形成非易失性电阻氧化物存储器阵列的方法包括在衬底上形成多个导电字线或导电位线。 含金属氧化物的材料形成在多条所述一条字线或位线中。 在多个所述一条字线或位线之间提供一系列细长的沟槽。 多个自组装嵌段共聚物线形成在沟槽中的各个内，与沟槽侧壁之间对准并且在沟槽侧壁之间形成。 从所述多个自组装嵌段共聚物线路提供多个导电字线或导电位线，以形成包含所述金属氧化物的材料的单独可编程的结，其中字线和位线彼此交叉。

公开(公告)号：US20110057161A1

公开(公告)日：2011-03-10

申请号：US12557315

申请日：2009-09-10

申请人： Gurtej Sandhu ,  John Smythe ,  Jun Liu

发明人： Gurtej Sandhu ,  John Smythe ,  Jun Liu

IPC分类号： H01L47/00 ,  H01L21/06

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

摘要： Various embodiments described herein provide a memory device including a variable resistance material having a thermally isolating and electrically conductive isolation region arranged between the variable resistance material and an electrode to allow for efficient heating of the variable resistance material by a programming current. An electrically and thermally isolating isolation region may be arranged around the variable resistance material.

摘要翻译： 本文描述的各种实施例提供了一种包括可变电阻材料的存储器件，该可变电阻材料具有布置在可变电阻材料和电极之间的隔热和导电隔离区域，以允许通过编程电流有效地加热可变电阻材料。 可以在可变电阻材料周围布置电隔离隔离区域。

公开(公告)号：US07737039B2

公开(公告)日：2010-06-15

申请号：US11933664

申请日：2007-11-01

申请人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

发明人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

IPC分类号： H01L21/311

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

摘要翻译： 公开了诸如涉及增加集成电路中的隔离特征的密度的方法。 还公开了与该方法相关联的结构。 在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。 互连可以由间距倍增形成。 为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。 可选择定义的材料中的特征被修剪到期望的尺寸。 间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。 去除可选择定义的材料以留下由间隔物材料限定的掩模。 由间隔物材料限定的图案可以转移到基底上，以形成间距接触。 在一些实施例中，上电触点可用于电接触衬底中的导电互连。

公开(公告)号：US20090317540A1

公开(公告)日：2009-12-24

申请号：US12141559

申请日：2008-06-18

申请人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

发明人： Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

IPC分类号： B05D5/12

CPC分类号： H01L27/101 ,  H01L21/0271 ,  Y10S438/947

摘要： A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

摘要翻译： 形成非易失性电阻氧化物存储器阵列的方法包括在衬底上形成多个导电字线或导电位线。 含金属氧化物的材料形成在多条所述一条字线或位线中。 在多个所述一条字线或位线之间提供一系列细长的沟槽。 多个自组装嵌段共聚物线形成在沟槽中的各个内，与沟槽侧壁之间对准并且在沟槽侧壁之间形成。 从所述多个自组装嵌段共聚物线路提供多个导电字线或导电位线，以形成包含所述金属氧化物的材料的单独可编程的结，其中字线和位线彼此交叉。

公开(公告)号：US20090272960A1

公开(公告)日：2009-11-05

申请号：US12114096

申请日：2008-05-02

申请人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L45/00

CPC分类号： H01L45/04 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material. The forming thereof includes etching through the conductive material to form opposing laterally outermost conductive edges of said conductive material in the one planar cross section at the conclusion of said etching which are received laterally outward of the opposing laterally outermost edges of the first conductive electrode in the one planar cross section.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 第一导电电极在一个平面横截面中具有垂直最外表面和在最外表面处的相对的横向最外边缘。 在第一导电电极上形成包含多电阻态金属氧化物的材料。 导电材料沉积在多电阻状态的含金属氧化物的材料上。 包含导电材料的存储单元的第二导电电极被接收在多电阻状态的含金属氧化物的材料上。 其形成包括通过导电材料的蚀刻，以在所述蚀刻结束时在一个平面截面中形成所述导电材料的相对的横向最外面的导电边缘，其在第一导电电极的相对的横向最外边缘的横向外侧接收 一个平面截面。

公开(公告)号：US08399952B2

公开(公告)日：2013-03-19

申请号：US13103162

申请日：2011-05-09

申请人： Bhaskar Srinivasan ,  Vassil Antonov ,  John Smythe

发明人： Bhaskar Srinivasan ,  Vassil Antonov ,  John Smythe

IPC分类号： H01L21/00

CPC分类号： H01L28/75 ,  C23C16/404 ,  C23C16/409 ,  C23C16/45527 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/0228 ,  H01L28/56 ,  H01L28/65

摘要： Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source.

摘要翻译： 钌氧化钌提供钌导体和锶钛氧化物电介质之间的有效界面。 锶氧化钌的形成包括使用原子层沉积形成氧化锶，随后退火氧化锶以形成氧化锶锶。 使用水作为氧源来进行氧化锶的第一原子层沉积，然后使用臭氧作为氧源，随后用氧化锶沉积氧化锶。

公开(公告)号：US20120235108A1

公开(公告)日：2012-09-20

申请号：US13486678

申请日：2012-06-01

申请人： John Smythe

发明人： John Smythe

IPC分类号： H01L45/00

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

摘要： A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.

摘要翻译： 一种可变电阻存储单元结构及其形成方法。 该方法包括形成第一电极，在第一电极上形成绝缘材料，在绝缘材料中形成通孔以暴露第一电极的表面，在气体簇离子束中形成通孔内的加热材料，形成可变电阻 并且形成第二电极，使得加热材料和可变电阻材料设置在第一和第二电极之间。

公开(公告)号：US08236372B2

公开(公告)日：2012-08-07

申请号：US12483455

申请日：2009-06-12

申请人： Rishikesh Krishnan ,  John Smythe ,  Vishwanath Bhat ,  Noel Rocklein ,  Bhaskar Srinivasan ,  Jeff Hall ,  Chris Carlson

发明人： Rishikesh Krishnan ,  John Smythe ,  Vishwanath Bhat ,  Noel Rocklein ,  Bhaskar Srinivasan ,  Jeff Hall ,  Chris Carlson

IPC分类号： B05D5/12

CPC分类号： H01G4/12 ,  H01G4/1272 ,  H01G4/33 ,  H01L28/40

摘要： Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10−7 amps/cm2 at from −1.1V to +1.1V.

摘要翻译： 公开了形成电容器的电容器和方法，其包括内部导电金属电容器电极和外部导电金属电容器电极。 电容器电介质区域被容纳在内导电金属电容电极和外导电金属电容器电极之间，并且具有不大于150埃的厚度。 公开了厚度和关系的材料的各种组合，其相互之间可以实现和导致电介质区域的介电常数k至少为35，而在-1.1V至-1.0V的范围内漏电流不大于1×10-7Aps / cm 2 + 1.1V。

公开(公告)号：US08223539B2

公开(公告)日：2012-07-17

申请号：US12693936

申请日：2010-01-26

申请人： John Smythe ,  Gurtej S. Sandhu

发明人： John Smythe ,  Gurtej S. Sandhu

IPC分类号： G11C11/34

CPC分类号： H01L45/165 ,  G11C13/0007 ,  G11C2213/56 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1641 ,  H01L45/1683

摘要： The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

摘要翻译： 本公开包括GCIB处理的电阻性装置，利用GCIB处理的电阻性装置（例如，作为开关，存储器单元）的装置以及用于形成经GCIB处理的电阻装置的方法。 形成GCIB处理的电阻性器件的一种方法包括形成下电极，并在下电极上形成氧化物材料。 将氧化物材料暴露于气体簇离子束（GCIB），直到氧化物材料的第一部分的电阻相对于氧化物材料的第二部分的电阻发生变化。 上电极形成在第一部分上。