公开(公告)号：US20080023758A1

公开(公告)日：2008-01-31

申请号：US11863556

申请日：2007-09-28

申请人： Masaki Shiraishi ,  Noboru Akiyama ,  Tomoaki Uno ,  Nobuyoshi Matsuura

发明人： Masaki Shiraishi ,  Noboru Akiyama ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L29/78

CPC分类号： G05F3/08 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/16 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7835 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/73221 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85375 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M7/003 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.

摘要翻译： 本发明的目的是减少电源电路中的主电路的寄生电感。 本发明提供一种非绝缘DC-DC转换器，其具有用于高侧开关的功率MOSFET和用于低侧开关的功率MOS.FET串联连接的电路。 在非绝缘DC-DC转换器中，用于高侧开关的功率MOS.FET由p沟道垂直MOSFET形成，低边开关的功率MOS.FET由n沟道垂直 MOS.FET。 因此，形成有用于高侧开关的功率MOS.FET和形成有用于低侧开关的功率MOSFET的半导体芯片的半导体芯片安装在相同的芯片焊盘上，并通过 芯片垫

公开(公告)号：US20070200537A1

公开(公告)日：2007-08-30

申请号：US11624767

申请日：2007-01-19

申请人： Noboru Akiyama ,  Takayuki Hashimoto ,  Masaki Shiraishi ,  Tetsuya Kawashima ,  Koji Tateno ,  Nobuyoshi Matsuura

发明人： Noboru Akiyama ,  Takayuki Hashimoto ,  Masaki Shiraishi ,  Tetsuya Kawashima ,  Koji Tateno ,  Nobuyoshi Matsuura

IPC分类号： G05F1/10 ,  H02J3/12

CPC分类号： H01L25/16 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/05554 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H02M3/1588 ,  H03K17/08142 ,  H03K17/162 ,  H03K17/6871 ,  H03K2217/0036 ,  Y02B70/1466 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A power supply capable of reducing loss of large current and high frequency. In an MCM for power supply in which a high-side power MOSFET chip, a low-side power MOSFET chip and a driver IC chip driving them are sealed in one sealing material (a capsulating insulation resin), a wiring length of a wiring DL connecting an output terminal of the driver IC chip to a gate terminal of the low-side power MOSFET chip or a source terminal is made shorter than a wiring length of a wiring DH connecting the output terminal of the driver IC chip to a gate terminal of the high-side power MOSFET chip or a source terminal. Further, the number of the wiring DL is made larger than the number of the wiring DH.

摘要翻译： 一种能够减少大电流和高频损耗的电源。 在用于电源的MCM中，高边功率MOSFET芯片，低边功率MOSFET芯片和驱动IC芯片驱动它们被密封在一个密封材料（封装绝缘树脂）中，布线DL的布线长度 将驱动IC芯片的输出端子与低边功率MOSFET芯片的栅极端子或源极端子连接的距离比连接驱动器IC芯片的输出端子的栅极端子的布线长度短 高端功率MOSFET芯片或源极端子。 此外，使布线数量DL大于布线数量DH。

公开(公告)号：US20070195563A1

公开(公告)日：2007-08-23

申请号：US11624837

申请日：2007-01-19

申请人： Masaki Shiraishi ,  Takayuki Hashimoto ,  Noboru Akiyama

发明人： Masaki Shiraishi ,  Takayuki Hashimoto ,  Noboru Akiyama

IPC分类号： H02M3/335

CPC分类号： H02M1/08 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H03K17/0822 ,  H03K17/165 ,  H03K17/166 ,  H03K17/6871 ,  H01L2924/00 ,  H01L2224/45099

摘要： In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.

摘要翻译： 在非隔离型DC / DC转换器中，从通过高侧MOSFET的主电路以外的部分施加驱动低侧MOSFET的栅极的低侧预驱动器的基准电位， 低侧MOSFET，使得低侧MOSFET的源极与预驱动器之间的寄生电感增加，而不增加主电路中的寄生电感的和，并且低侧MOSFET的栅极的负电位驱动 并且可以防止在不添加任何构件和改变驱动系统的情况下自启闭现象。

公开(公告)号：US20050237039A1

公开(公告)日：2005-10-27

申请号：US10524087

申请日：2003-08-08

申请人： Mutsumi Kikuchi ,  Noboru Akiyama ,  Hiroyuki Shoji ,  Fumio Murabayashi ,  Akihiko Kanouda ,  Takashi Sase ,  Koji Tateno

发明人： Mutsumi Kikuchi ,  Noboru Akiyama ,  Hiroyuki Shoji ,  Fumio Murabayashi ,  Akihiko Kanouda ,  Takashi Sase ,  Koji Tateno

IPC分类号： G05F1/40 ,  G11C5/14 ,  H01L27/06 ,  H01L27/08 ,  H02M3/156

CPC分类号： G11C5/147 ,  H01L27/0688 ,  H01L27/08 ,  H02M3/156 ,  H02M2001/007

摘要： A semiconductor device capable of achieving downsizing without reducing the power supply efficiency and capable of reducing switching noises and a memory card using the same are disclosed. The device comprises a plurality of stages of voltage booster circuits for potentially raising a power supply voltage up to a final output voltage, a voltage control unit for controlling an output voltage at a nearby location of the final stage, and one or more internal elements to which the final output voltage is supplied. A primary voltage booster circuit at the first stage includes an inductance element, a switching element, a diode and a driver circuit. At a metal core part of the inductance element, a metal wiring line is used, which was formed by use of a fabrication process of semiconductor integrated circuits, while employing for its core part an inter-wiring layer dielectric film that was formed using the fabrication process. In addition, the switching element and the diode are arranged so that portions thereof are disposed beneath the inductance element.

摘要翻译： 公开了能够实现小型化而不降低电源效率并且能够降低开关噪声的半导体器件和使用其的存储卡。 该装置包括用于潜在地提高最终输出电压的电源电压的多级升压电路，用于控制最后级的附近位置处的输出电压的电压控制单元和一个或多个内部元件 其提供最终输出电压。 第一级的初级升压电路包括电感元件，开关元件，二极管和驱动器电路。 在电感元件的金属芯部分，使用通过使用半导体集成电路的制造工艺形成的金属布线，同时使用其核心部分使用该制造形成的布线层电介质膜 处理。 此外，开关元件和二极管被布置成使得其部分设置在电感元件下方。

公开(公告)号：US6040827A

公开(公告)日：2000-03-21

申请号：US890994

申请日：1997-07-10

申请人： Kazuhiro Shiina ,  Koji Kawamoto ,  Masato Miura ,  Hitoshi Ohura ,  Shoichi Ozeki ,  Noboru Akiyama ,  Kunihoro Nunomura ,  Minehiro Nemoto ,  Masahiro Iwamura

发明人： Kazuhiro Shiina ,  Koji Kawamoto ,  Masato Miura ,  Hitoshi Ohura ,  Shoichi Ozeki ,  Noboru Akiyama ,  Kunihoro Nunomura ,  Minehiro Nemoto ,  Masahiro Iwamura

IPC分类号： G09G3/20 ,  G09G3/28 ,  G09G3/288 ,  G09G3/30 ,  H02P6/08 ,  G09G5/00

CPC分类号： H02P6/085 ,  G09G3/20 ,  G09G3/296 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0289 ,  G09G3/30

摘要： A driver circuit wherein a first switching element and a second switching element are totem-pole-connected, wherein the totem pole connection is connected at its one end, node and other end with a power source, an output to a load and a reference potential, respectively, wherein the first switching element is connected between the one end and the node, wherein the second switching element is connected between the node and the other end, and wherein a third switching element is connected between the one end of the totem pole connection and the control terminal of the first switching element.

摘要翻译： 一种驱动器电路，其中第一开关元件和第二开关元件是图腾极连接的，其中图腾柱连接在其一端，节点和另一端与电源连接，输出到负载和参考电位 ，其中所述第一开关元件连接在所述一端和所述节点之间，其中所述第二开关元件连接在所述节点和所述另一端之间，并且其中第三开关元件连接在所述图腾柱连接的所述一端 和第一开关元件的控制端子。

公开(公告)号：US5627707A

公开(公告)日：1997-05-06

申请号：US523039

申请日：1995-09-01

申请人： Noboru Akiyama ,  Katsumi Kameda

发明人： Noboru Akiyama ,  Katsumi Kameda

IPC分类号： G11B23/03

CPC分类号： G11B23/0303 ,  G11B23/0307 ,  G11B23/0308 ,  G11B23/0316

摘要： A case supporting structure has four support pins provided in a disk player, a pair of the support pins having two small size locating pins on upper surfaces of the support pins, and four support seat places formed on the lower shell half. A pair of the support seat places respectively have a circular opening to receive one of the locating pins and an elliptic opening to receive loosely another locating pin. The support seat places on the lower shell half are of small smooth areas to be supported on the support pins.

摘要翻译： 壳体支撑结构具有设置在盘播放器中的四个支撑销，一对支撑销在支撑销的上表面上具有两个小尺寸定位销，以及形成在下壳半部上的四个支撑座位。 一对支撑座位分别具有圆形开口以接收一个定位销和一个椭圆形开口以松动地接收另一个定位销。 支撑座位于下半壳体上的小平滑区域被支撑在支撑销上。

公开(公告)号：US5463639A

公开(公告)日：1995-10-31

申请号：US234043

申请日：1994-04-28

申请人： Tetsuya Koishi ,  Noboru Akiyama ,  Yasuto Kumai

发明人： Tetsuya Koishi ,  Noboru Akiyama ,  Yasuto Kumai

IPC分类号： G06F11/24 ,  G01R31/28

CPC分类号： G06F11/24

摘要： An automatic pattern synchronizing circuit re-times the phase differences between clocks, thereby adjusting test pattern outputs from a device under test. The automatic pattern synchronizing circuit includes a reference voltage generator for providing a threshold voltage, a comparator for converting an input signal into a rectangular signal, a flip-flop, a pattern-counter part for counting a signal from the flip-flop and a control part for setting the threshold voltage in the comparator. The automatic pattern synchronizing circuit automatically synchronizes voltage patterns. In particular, the high and low voltage levels of the input waveform are automatically measured and the optimum threshold voltage is automatically set.

摘要翻译： 自动图案同步电路对时钟之间的相位差进行重新计时，从而调整来自被测器件的测试图案输出。 自动图案同步电路包括用于提供阈值电压的参考电压发生器，用于将输入信号转换为矩形信号的比较器，触发器，用于对来自触发器的信号进行计数的图形计数器部分和控制 用于设置比较器中的阈值电压的部分。 自动模式同步电路自动同步电压模式。 特别地，自动测量输入波形的高低电压电平，并自动设置最佳阈值电压。

公开(公告)号：US5051857A

公开(公告)日：1991-09-24

申请号：US373020

申请日：1989-06-28

申请人： Noboru Akiyama

发明人： Noboru Akiyama

IPC分类号： G11B23/03

CPC分类号： G11B23/0307 ,  G11B23/0308 ,  G11B23/0316

摘要： A disc cartridge has a spindle hole, a head insertion hole and a shutter for opening and closing the two holes, the shutter being urged by an elastic member and having an elongated arm whose distal end engages with a guide groove formed on a guide portion of the cartridge.

公开(公告)号：US4701918A

公开(公告)日：1987-10-20

申请号：US737467

申请日：1985-05-24

申请人： Takayuki Nakajima ,  Tetsuo Aoki ,  Katsumi Kobayashi ,  Noboru Akiyama

发明人： Takayuki Nakajima ,  Tetsuo Aoki ,  Katsumi Kobayashi ,  Noboru Akiyama

IPC分类号： G01R31/3177 ,  G06F11/25 ,  G01R31/28 ,  G06F11/00

CPC分类号： G01R31/3177 ,  G06F11/25

摘要： A logic analyzer applies test pattern signals from a pattern generator to a circuit under test and sequentially reads logic outputs into a memory. The output from the circuit under test when it reaches a predetermined logic state is input as an external control signal into the logic analyzer. A change command is generated from the pattern generator in relation to the generation of the test pattern signal. When the change command and the external control signal are obtained at the same time, and flow of the generation of the test pattern signals is changed to a predetermined flow.

摘要翻译： 逻辑分析仪将来自模式发生器的测试模式信号应用于被测电路，并将逻辑输出顺序读入存储器。 当达到预定逻辑状态时，被测电路的输出作为外部控制信号输入到逻辑分析仪中。 相对于测试图形信号的生成，从图案生成器生成变更命令。 当同时获得改变命令和外部控制信号时，将测试图形信号的产生流程改变为预定流量。

公开(公告)号：US09076601B2

公开(公告)日：2015-07-07

申请号：US13498953

申请日：2010-09-29

申请人： Takanori Yamashita ,  Hirohisa Akita ,  Noboru Akiyama ,  Masataka Okushita

发明人： Takanori Yamashita ,  Hirohisa Akita ,  Noboru Akiyama ,  Masataka Okushita

IPC分类号： G01R31/28 ,  G01R31/08 ,  H01H31/12 ,  G01R31/06 ,  H01G11/14 ,  H01G11/06 ,  H01G11/80 ,  H01M10/48 ,  H01M10/04 ,  H01M10/0525

CPC分类号： G01R31/3641 ,  G01R31/025 ,  G01R31/12 ,  G01R31/1263 ,  H01G11/06 ,  H01G11/14 ,  H01G11/20 ,  H01G11/80 ,  H01G11/82 ,  H01M10/04 ,  H01M10/0525 ,  H01M10/48 ,  Y02E60/13 ,  Y10T29/49004

摘要： A method for manufacturing an electrochemical cell includes housing a main cell body in an outer packaging body of packaging material formed by laminating a metal foil layer and a heat-sealable resin layer, provided the tip ends of a first metal terminal and a second metal terminal are protruding outside the outer packaging body, heat-sealing a peripheral edge portion of the outer packaging body so the outer packaging body has the first and second terminals protruding; applying a voltage between the first terminal and the foil layer or between the second terminal and the foil layer; and inspecting for insulation failure from a short circuit between the first or second terminal and the foil layer or from a crack in the heat-sealable resin layer, based on a variation of a voltage held between the one of the metal terminals and the metal foil layer after halting the voltage.

摘要翻译： 一种电化学电池的制造方法，其特征在于，在第一金属端子和第二金属端子的前端设置有通过层叠金属箔层和可热封树脂层而形成的包装材料的外包装体中的主电池体 在外包装体的外侧突出，热封外包装体的周缘部，使得外包装体具有突出的第一和第二端子; 在第一端子和箔层之间或第二端子和箔层之间施加电压; 并且基于金属端子和金属箔之间保持的电压的变化来检查第一或第二端子与箔层之间的短路或可热封树脂层中的裂纹的绝缘故障 停止电压后的层。