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公开(公告)号：US09971666B2
公开(公告)日：2018-05-15
申请号：US15060221
申请日：2016-03-03
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee Mishra , Richard Dominic Wietfeldt , James Lionel Panian , George Alan Wiley , Amit Gil
CPC classification number: G06F11/3051 , G06F1/3209 , G06F1/3278 , G06F9/4418 , G06F11/3041 , G06F15/17 , G06F15/7807 , Y02D10/157
Abstract: System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a bit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message. Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.
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42.发明授权公开(公告)号：US09812057B2
公开(公告)日：2017-11-07
申请号：US14818675
申请日：2015-08-05
Applicant: QUALCOMM Incorporated
Inventor： George Alan Wiley
CPC classification number: G09G3/2092 , G06F3/0412 , G06F13/4072 , G09G3/20 , G09G5/008 , G09G2300/0426 , G09G2300/043 , G09G2300/0809 , G09G2310/08 , G09G2320/0209 , G09G2320/0223 , G09G2370/00 , H04L25/0274 , H04L25/0278 , H04L25/03
Abstract: A termination circuit can include an impedance component. A first port can be configured to be connected to a first node. The first node can be a node of a conductor of a cable. A first end of the cable can be configured to be connected to a signal producing circuit. A second end of the cable can be configured to be connected to a first end of a trace disposed on a substrate of a display device. A second end of the trace can be connected to a display driver integrated circuit (DDIC). The DDIC can lack a termination impedance component internal to the DDIC to provide a line termination function for a serial interface with the signal producing circuit. A second port can be configured to be connected to a second node. The impedance component can be connected between the first port and the second port.
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公开(公告)号：US09711041B2
公开(公告)日：2017-07-18
申请号：US13797272
申请日：2013-03-12
Applicant: QUALCOMM Incorporated
Inventor： George Alan Wiley , Glenn D. Raskin
CPC classification number: G08C19/16 , H04L25/0272
Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A data transfer method comprises encoding data and control signals in a sequence of symbols to be transmitted on a plurality of connectors, and transmitting the sequence of symbols on the plurality of connectors. Each symbol may be transmitted using a combination of a phase state of a first pair of connectors, a polarity of a second pair of connectors, and a selection of at least one undriven connector. Transmission of each symbol in the sequence of symbols may cause a change of state for at least one of the plurality of connectors.
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公开(公告)号：US09639499B2
公开(公告)日：2017-05-02
申请号：US14302359
申请日：2014-06-11
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Joseph Cheung
IPC: G06F13/42 , G06F13/364 , H04L7/033
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/4282 , G06F13/4295 , H04L7/0331
Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.
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公开(公告)号：US20170117979A1
公开(公告)日：2017-04-27
申请号：US15253020
申请日：2016-08-31
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley
CPC classification number: H04J3/0605 , G06F13/42 , G06F13/4282 , G06F21/85 , H04L1/0061 , H04L9/0662 , H04L25/03866 , H04L45/74 , Y02D10/14 , Y02D10/151
Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. A method includes initializing a scrambler with a first pseudo-random binary sequence (PRBS) seed word after receiving a first sync word, the first sync word preceding a first packet, using the scrambler and the first PRBS seed word to scramble a first copy of a packet header that succeeds the first sync word in the first packet, initializing the scrambler with a second PRBS seed word after scrambling the first copy of the packet header, the second sync word succeeding the first copy of the packet header in the first packet, using the scrambler and the second PRBS seed word to scramble a second copy of the packet header that succeeds the second sync word in the first packet.
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Patent Agency Ranking
46.发明授权Method and apparatus to enable multiple masters to operate in a single master bus architecture 有权使多个主机能够在单个主总线架构中运行的方法和装置公开(公告)号：US09519603B2
公开(公告)日：2016-12-13
申请号：US14480540
申请日：2014-09-08
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , Richard Dominic Wietfeldt , George Alan Wiley
IPC: G06F13/378 , G06F13/36 , G06F13/24 , G06F13/362
CPC classification number: G06F13/378 , G06F13/24 , G06F13/36 , G06F13/362 , G06F2213/3602
Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.
Abstract translation: 为了通过支持单个主器件的总线架构来容纳多个主器件，为非激活主器件提供了通过共享的单线IRQ总线触发IRQ信号的机制。 然后当前主机通过共享数据总线轮询其他无效主设备，以确定哪个无效主设备正在断言IRQ信号。 当识别出断言无效的主设备时，当前的主设备将数据总线的控制权授予新的主设备，从而使非活动主设备成为新的主主设备。
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公开(公告)号：US20160226734A1
公开(公告)日：2016-08-04
申请号：US15097027
申请日：2016-04-12
Applicant: QUALCOMM Incorporated
Inventor： Shree Krishna Pandey , Arun Chandra Kundu , George Alan Wiley , Chulkyu Lee
CPC classification number: H04L43/087 , G06F13/40 , H04B3/00 , H04B3/462 , H04B3/542 , H04L7/0041 , H04L25/0264 , H04L25/14
Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.
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48.发明申请METHOD AND APPARATUS TO ENABLE MULTIPLE MASTERS TO OPERATE IN A SINGLE MASTER BUS ARCHITECTURE 审中-公开使用多个主机在单个主总线架构中运行的方法和装置公开(公告)号：US20160217090A1
公开(公告)日：2016-07-28
申请号：US15087535
申请日：2016-03-31
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , Richard Dominic Wietfeldt , George Alan Wiley
IPC: G06F13/364 , G06F13/42 , G06F13/26
CPC classification number: G06F13/364 , G06F13/24 , G06F13/26 , G06F13/362 , G06F13/4256 , G06F13/426
Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to assert an in-band IRQ. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.
Abstract translation: 为了通过支持单个主设备的总线架构来容纳多个主机，为非活动主设备提供了一种机制来断言带内IRQ。 然后当前主机通过共享数据总线轮询其他无效的主设备，以确定哪个非活动主设备正在断言IRQ。 当识别出断言无效的主设备时，当前的主设备将数据总线的控制权授予新的主设备，从而使非活动主设备成为新的主主设备。
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49.发明授权Transcoding method for multi-wire signaling that embeds clock information in transition of signal state 有权用于在信号状态转换中嵌入时钟信息的多线信号的转码方法公开(公告)号：US09337997B2
公开(公告)日：2016-05-10
申请号：US14199898
申请日：2014-03-06
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Chulkyu Lee , Joseph Cheung
IPC: H04L27/00 , H04L7/033 , H04L7/027 , H04L7/00 , H04L25/49 , H04L25/493 , H03K5/1252 , H03K5/1534 , H04L25/14 , H04L25/02
CPC classification number: H04L7/033 , H03K5/1252 , H03K5/1534 , H04L7/0066 , H04L7/027 , H04L25/0272 , H04L25/14 , H04L25/49 , H04L25/4906 , H04L25/493
Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.
Abstract translation: 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换编号从一组顺序符号编号转换成顺序符号。 顺序符号号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播扩展到多条n线，其中时钟信号被有效地嵌入在原始符号的传输中，因为从转换数转换为顺序符号，保证没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零的差分电压。
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公开(公告)号：US09294202B1
公开(公告)日：2016-03-22
申请号：US14494998
申请日：2014-09-24
Applicant: QUALCOMM Incorporated
Inventor： Richard Dominic Wietfeldt , George Chrisikos , George Alan Wiley
CPC classification number: H04B15/02 , H04B1/123 , H04B17/23 , H04W72/082
Abstract: Aspects of adjusting application parameters for interference mitigation are disclosed. In one aspect, a computing device is provided that employs a control system configured to detect and mitigate electromagnetic interference (EMI) generated within the computing device. More specifically, the control system is configured to detect possible EMI conditions and adjust parameters within the computing device to mitigate such EMI. In this manner, the computing device includes an aggressor application and a victim receiver. The control system is configured to analyze performance tradeoffs based on an acceptable performance level of the aggressor application and the performance degradation experienced by the victim receiver. Based on such analysis, the control system is configured to adjust parameters associated with the aggressor application to mitigate the EMI. Thus, the control system provides designers with an additional tool that may reduce the performance degradation of the victim receiver attributable to the EMI.
Abstract translation: 公开了调整用于干扰减轻的应用参数的方面。 在一个方面，提供了一种计算设备，其采用配置成检测和减轻在计算设备内产生的电磁干扰（EMI）的控制系统。 更具体地，控制系统被配置为检测可能的EMI条件并且调整计算设备内的参数以减轻这样的EMI。 以这种方式，计算设备包括攻击者应用和受害者接收器。 控制系统被配置为基于攻击者应用的可接受的性能水平和受害者接收器所经历的性能下降来分析性能权衡。 基于这种分析，控制系统被配置为调整与侵略者应用相关联的参数以减轻EMI。 因此，控制系统为设计人员提供了一种附加工具，可以降低由于EMI引起的受害接收机的性能下降。
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