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    Semiconductor device
    41.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09496220B2

    公开(公告)日：2016-11-15

    申请号：US14328458

    申请日：2014-07-10

    Applicant: Renesas Electronics Corporation

    Inventor： Yasutaka Nakashiba

    IPC: H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065

    CPC classification number: H01L23/5227 ,  H01L23/48 ,  H01L23/538 ,  H01L23/645 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor formed in the multilayer interconnect, and a second spiral inductor formed in the multilayer interconnect. The first spiral inductor and the second spiral inductor collectively include a line, the line being spirally wound in a first direction in the first spiral inductor toward outside of the first spiral inductor, and being spirally wound in a second direction in the second spiral inductor toward inside of the second spiral inductor. The first direction and the second direction are opposite directions.

    Abstract translation: 半导体器件包括具有多层互连的半导体芯片，形成在多层互连中的第一螺旋感应电感器和形成在多层互连中的第二螺旋电感器。 第一螺旋电感器和第二螺旋电感器共同地包括一条线，该线路沿着第一方向在第一螺旋电感器中朝向第一螺旋电感器的外侧螺旋地卷绕，并且在第二螺旋电感器中沿第二方向螺旋地卷绕， 内部的第二个螺旋电感。 第一方向和第二方向是相反的方向。

    Semiconductor device
    42.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09385230B2

    公开(公告)日：2016-07-05

    申请号：US14804819

    申请日：2015-07-21

    Applicant: Renesas Electronics Corporation

    Inventor： Akihiro Shimomura ,  Yutaka Akiyama ,  Saya Shimomura ,  Yasutaka Nakashiba

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/808 ,  H01L29/40 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06

    CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

    Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

    Abstract translation: 一种半导体器件，包括第一导体层，形成在第一导体层上的第二导体层，形成在第二导体层上的第三导体层，通过第三导体层并形成在第二导体层中的栅极沟槽， 形成在栅极沟槽的内壁上的第一绝缘膜，形成在栅极沟槽的内壁上的第二绝缘膜，形成在栅极沟槽中的第一掩埋导体层，形成在栅极沟槽中的栅电极，第四绝缘膜 在第一掩埋导体层的下端形成的第二导电类型的导体层和栅极沟槽的下端，以及形成在第三导体层上的第一导电类型的第五导电层。 第一绝缘膜比第二绝缘膜厚。

    Semiconductor device
    43.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09299772B2

    公开(公告)日：2016-03-29

    申请号：US14715641

    申请日：2015-05-19

    Applicant: Renesas Electronics Corporation

    Inventor： Yoshiyuki Sato ,  Yasutaka Nakashiba

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/528

    CPC classification number: H01L29/063 ,  H01L23/528 ,  H01L28/20 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device in which the concentration of an electric field is suppressed in a region overriding a drain region and a source region. A drain region is formed in a first region, a source region is formed in a second region. A field oxide film surrounds the first region in a plan view. A metal interconnect situated over a field oxide film. The metal interconnect formed of a metal having an electric resistivity at 25° C. of 40 μΩ·cm or more and 200 μΩ·cm or less. Further, the metal interconnect is repeatedly provided spirally in a direction along the edges of the first region. Further, the metal interconnect is electrically connected at the innermost circumference with the drain region, and is connected at the outermost circumference to the source region or a ground potential.

    Abstract translation: 在超过漏极区域和源极区域的区域中抑制电场的浓度的半导体器件。 漏极区域形成在第一区域中，源区域形成在第二区域中。 在平面图中，场氧化膜围绕第一区域。 位于场氧化膜上方的金属互连。 在25℃下的电阻率为40μΩ·cm〜0.8cm以上且200μΩ·cm以上的金属构成的金属配线。 此外，金属互连在沿着第一区域的边缘的方向上螺旋地重复设置。 此外，金属互连件在最内周与漏区电连接，并且在最外周连接到源极区域或接地电位。

    Semiconductor device
    44.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08907460B2

    公开(公告)日：2014-12-09

    申请号：US14012324

    申请日：2013-08-28

    Applicant: Renesas Electronics Corporation

    Inventor： Takasuke Hashimoto ,  Shinichi Uchida ,  Yasutaka Nakashiba ,  Takatsugu Nemoto

    IPC: H01L23/552 ,  H01L23/522 ,  H01L23/58 ,  H05K9/00

    CPC classification number: H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L2924/0002 ,  H05K9/00 ,  H01L2924/00

    Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.

    Abstract translation: 为了抑制由电感器引起的噪声泄漏到外部，并且还被配置为使得磁场强度变化到达电感器。 电感器在平面视图中围绕内部电路，并且还与内部电路电连接。 电感器的上侧由上屏蔽部分覆盖，电感器的下侧由下屏蔽部分覆盖。 上部屏蔽部分通过使用多层布线层形成。 上部屏蔽部分具有多个第一开口。 第一个开口在平面视图中与电感器重叠。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    45.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20140312440A1

    公开(公告)日：2014-10-23

    申请号：US14244820

    申请日：2014-04-03

    Applicant: Renesas Electronics Corporation

    Inventor： Yutaka Akiyama ,  Yasutaka Nakashiba

    IPC: G01L1/22

    CPC classification number: G01L9/005 ,  G01L9/0055 ,  H01L29/84 ,  H01L41/113

    Abstract: An object of the present invention is to suppress an error in the value detected by a pressure sensor, which may be caused when environmental temperature varies. A semiconductor substrate has a first conductivity type. A semiconductor layer is formed over a first surface of the semiconductor substrate. Each of resistance parts has a second conductivity type, and is formed in the semiconductor layer. The resistance parts are spaced apart from each other. A separation region is a region of the first conductivity type formed in the semiconductor layer, and electrically separates the resistance parts from each other. A depressed portion is formed in a second surface of the semiconductor substrate, and overlaps the resistance parts, when viewed planarly. The semiconductor layer is an epitaxial layer.

    Abstract translation: 本发明的目的是抑制当环境温度变化时可能引起的压力传感器检测到的值的误差。 半导体衬底具有第一导电类型。 在半导体衬底的第一表面上形成半导体层。 每个电阻部分具有第二导电类型，并且形成在半导体层中。 电阻部分彼此间隔开。 分离区域是在半导体层中形成的第一导电类型的区域，并且使电阻部分彼此电分离。 在半导体衬底的第二表面中形成凹陷部分，并且当平面地观察时，与电阻部分重叠。 半导体层是外延层。

    SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND SIGNAL TRANSMITTING/RECEIVING METHOD USING THE SEMICONDUCTOR DEVICE
    46.
    发明申请
    SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND SIGNAL TRANSMITTING/RECEIVING METHOD USING THE SEMICONDUCTOR DEVICE 有权
    半导体器件及其制造方法以及使用半导体器件的信号发送/接收方法

    公开(公告)号：US20140225221A1

    公开(公告)日：2014-08-14

    申请号：US14255270

    申请日：2014-04-17

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yasutaka Nakashiba

    IPC: H01L49/02

    CPC classification number: H01L28/10 ,  G01R31/2886 ,  G01R31/3025 ,  G01R31/303

    Abstract: A semiconductor device includes a semiconductor chip including a main surface, an internal circuit including a plurality of transistors, formed on the main surface, a bonding pad electrically connected to the internal circuit, formed on the main surface, an inductor for communicating an external device in a non-contact manner, formed on the main surface, and a seal ring formed along an outer peripheral edge of the semiconductor chip to surround the internal circuit and the bonding pad in a plan view. The inductor has a configuration to surround the internal circuit and the bonding pad in the plan view and along the seal ring. The inductor is arranged inside the seal ring.

    Abstract translation: 半导体器件包括：半导体芯片，其包括主表面，包括形成在主表面上的多个晶体管的内部电路，形成在主表面上的与内部电路电连接的焊盘，用于连通外部设备的电感器 以非接触方式形成在主表面上，以及沿着半导体芯片的外周边缘形成的密封环，以平面图包围内部电路和接合焊盘。 电感器具有在平面图和密封环中围绕内部电路和接合焊盘的构造。 电感器布置在密封环的内部。

    Semiconductor device
    49.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12142679B2

    公开(公告)日：2024-11-12

    申请号：US17722778

    申请日：2022-04-18

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Makoto Koshimizu ,  Yasutaka Nakashiba

    IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

    Abstract: In semiconductor device, a field plate portion having a high concentration p-type semiconductor region, a low concentration p-type semiconductor region having a lower impurity concentration than the high concentration p-type semiconductor region and a high concentration n-type semiconductor region is provided. Then, the high concentration p-type semiconductor region is electrically connected to the source region while the high concentration n-type semiconductor region is electrically connected to the drain region.

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