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    MEMORY CIRCUIT
    41.
    发明申请
    MEMORY CIRCUIT 有权
    存储器电路

    公开(公告)号：US20140313827A1

    公开(公告)日：2014-10-23

    申请号：US14318841

    申请日：2014-06-30

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takuro Ohmaru

    IPC: G11C14/00

    CPC classification number: G11C14/0018 ,  G11C5/14 ,  G11C11/34 ,  G11C11/41 ,  G11C14/00 ,  G11C14/0063 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1207 ,  H01L29/788 ,  H01L29/792

    Abstract: The present invention provides a memory circuit in which, while the power is not supplied, a data signal that has been held in a memory section corresponding to a volatile memory can be held in a capacitor in a memory section corresponding to a nonvolatile memory. In the nonvolatile memory section, a transistor whose channel is formed in an oxide semiconductor layer allows a signal to be held in the capacitor for a long period. Thus, the memory circuit can hold a logic state (data signal) even while the power supply is stopped. A potential applied to a gate of the transistor whose channel is formed in an oxide semiconductor layer is raised by a booster circuit provided between a wiring for carrying power supply potential and the gate of the transistor, allowing a data signal to be held even by one power supply potential without malfunction.

    Abstract translation: 本发明提供了一种存储电路，其中在不提供电力的情况下，已经保存在与易失性存储器相对应的存储器部分中的数据信号可以被保存在与非易失性存储器相对应的存储器部分中的电容器中。 在非易失性存储器部分中，其沟道形成在氧化物半导体层中的晶体管允许信号被长时间保持在电容器中。 因此，即使在电源停止的情况下，存储电路也可以保持逻辑状态（数据信号）。 施加到其沟道形成在氧化物半导体层中的晶体管的栅极的电位由设置在用于承载电源电位的布线和晶体管的栅极之间的升压电路升高，允许数据信号被保持为一个 电源电位无故障。

    MEMORY CIRCUIT AND MEMORY DEVICE
    42.
    发明申请
    MEMORY CIRCUIT AND MEMORY DEVICE 有权

    公开(公告)号：US20130135943A1

    公开(公告)日：2013-05-30

    申请号：US13683257

    申请日：2012-11-21

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takuro Ohmaru

    IPC: G11C7/12

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/00 ,  G11C11/412

    Abstract: To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that controls rewrite and read of the first data stored in the latch unit by being turned on or off in response to the control signal, and a second switch unit that controls rewrite and read of the second data stored in the latch unit by being turned on or off in response to the control signal. The latch unit includes a first inverter and a second inverter. At least one of the first inverter and the second inverter includes a first field-effect transistor, and a second field-effect transistor that has the same conductivity type as the first field-effect transistor and has a gate potential controlled in accordance with the control signal.

    SEMICONDUCTOR DISPLAY DEVICE
    43.
    发明申请
    SEMICONDUCTOR DISPLAY DEVICE 有权
    半导体显示设备

    公开(公告)号：US20130134416A1

    公开(公告)日：2013-05-30

    申请号：US13686366

    申请日：2012-11-27

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tatsuji Nishijima ,  Seiichi Yoneda ,  Takuro Ohmaru ,  Jun Koyama

    IPC: H01L33/16

    CPC classification number: G09G3/3648 ,  G02F2001/136295 ,  G09G3/3614 ,  G09G3/3677 ,  G09G5/393 ,  G09G5/395 ,  G09G2300/0842 ,  G09G2310/0264 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2360/121 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869 ,  H01L33/16

    Abstract: In the case where a still image is displayed on a pixel portion having a pixel, for example, a driver circuit for controlling writing of an image signal having image data to the pixel portion stops by stopping supply of power supply voltage to the driver circuit, and writing of an image signal to the pixel portion is stopped. After the driver circuit stops, supply of power supply voltage to a panel controller for controlling the operation of the driver circuit and an image memory for storing the image data is stopped, and supply of power supply voltage to a CPU for collectively controlling the operation of the panel controller, the image memory, and a power supply controller for controlling supply of power supply voltage to a variety of circuits in a semiconductor display device is stopped.

    Abstract translation: 在静止图像显示在具有像素的像素部分的情况下，例如通过停止对驱动电路的电源电压的供给来停止将具有图像数据的图像信号写入到像素部分的驱动电路， 并且停止向像素部分写入图像信号。 在驱动器电路停止之后，停止向用于控制驱动器电路的操作的面板控制器的电源电压供给和用于存储图像数据的图像存储器，并且向CPU提供电源电压以集中地控制 停止面板控制器，图像存储器和用于控制对半导体显示装置中的各种电路的电源电压供给的电源控制器。

    Semiconductor device including photoelectric conversion element
    46.
    发明授权
    Semiconductor device including photoelectric conversion element 有权

    公开(公告)号：US11205669B2

    公开(公告)日：2021-12-21

    申请号：US15311261

    申请日：2015-05-27

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yuki Okamoto ,  Yoshiyuki Kurokawa ,  Hiroki Inoue ,  Takuro Ohmaru

    IPC: H01L27/146 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H01L31/075 ,  H04N5/225

    Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.

    Memory device and semiconductor device
    49.
    发明授权
    Memory device and semiconductor device 有权
    存储器件和半导体器件

    公开(公告)号：US09536592B2

    公开(公告)日：2017-01-03

    申请号：US15072432

    申请日：2016-03-17

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Naoaki Tsutsui ,  Atsuo Isobe ,  Wataru Uesugi ,  Takuro Ohmaru

    IPC: G11C11/24 ,  G11C11/4093 ,  G11C11/403 ,  G11C11/401

    CPC classification number: G11C11/4093 ,  G11C11/24 ,  G11C11/401 ,  G11C11/403

    Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

    Abstract translation: 存储器件包括：第一存储器电路，包括硅晶体管，包括硅晶体管的选择电路和包括氧化物半导体晶体管和存储电容器的第二存储器电路，其中存储电容器的一个端子连接到两个 氧化物半导体晶体管串联连接，第二存储电路的输出连接到选择电路的第二输入端，第二存储电路的输入端连接到选择电路的第一输入端或输出端 的第一存储器电路。

    Semiconductor Device
    50.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20150263728A1

    公开(公告)日：2015-09-17

    申请号：US14638250

    申请日：2015-03-04

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takuro Ohmaru ,  Hidetomo KOBAYASHI

    IPC: H03K19/00 ,  H01L29/16 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H03K19/0008 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/16 ,  H01L29/7869

    Abstract: A dynamic logic circuit in which the number of elements is reduced, the layout area is reduced, the power loss is reduced, and the power consumption is reduced is provided. A semiconductor device including a dynamic logic circuit includes a first transistor in which a channel is formed in silicon and a second transistor in which a channel is formed in an oxide semiconductor. Here, a structure in which the second transistor is provided over the first transistor can be employed. A structure in which an insulating film is provided over the first transistor, and the second transistor is provided over the insulating film can be employed. A structure in which a top surface of the insulating film is planarized can be employed. A structure in which the second transistor has a region overlapping with the first transistor can be employed.

    Abstract translation: 一种动态逻辑电路，其中元件的数量减少，布局面积减小，功率损耗降低，功耗降低。 包括动态逻辑电路的半导体器件包括其中在硅中形成沟道的第一晶体管和其中在氧化物半导体中形成沟道的第二晶体管。 这里，可以采用在第一晶体管上设置第二晶体管的结构。 可以采用其中绝缘膜设置在第一晶体管上方并且第二晶体管设置在绝缘膜上的结构。 可以使用其中绝缘膜的顶表面被平坦化的结构。 可以采用其中第二晶体管具有与第一晶体管重叠的区域的结构。

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