公开(公告)号：US20210005533A1

公开(公告)日：2021-01-07

申请号：US16750579

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoukyung Cho ,  Daesuk Lee ,  Jinnam Kim ,  Taeseong Kim ,  Kwangjin Moon ,  Hakseung Lee

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole.

公开(公告)号：US10109665B2

公开(公告)日：2018-10-23

申请号：US15630063

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Kwangjin Moon ,  Seokho Kim ,  Sukchul Bang ,  Jin Ho An ,  Naein Lee

IPC: H01L27/146

Abstract: A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.

公开(公告)号：US08872351B2

公开(公告)日：2014-10-28

申请号：US13756833

申请日：2013-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangjin Moon ,  SuKyoung Kim ,  Kunsang Park ,  Byung Lyul Park ,  Sukchul Bang ,  Jin Ho An ,  Kyu-Ha Lee ,  Dosun Lee ,  Gilheyun Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/04 ,  H01L23/12 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode.

Abstract translation: 提供具有通孔的半导体器件及其制造方法。 所述方法可以包括形成至少部分地穿透基板的通孔，所述通孔具有设置在所述基板的顶表面上的入口，形成通孔绝缘层以保形地覆盖所述通孔的内表面，形成缓冲器 所述缓冲层由收缩性优于所述通孔绝缘层的材料形成，形成贯通电极以填充所述通孔，所述通孔设置在所述通孔绝缘层上， 与缓冲层一起凹陷基底的底表面以露出通孔。

公开(公告)号：US08691692B2

公开(公告)日：2014-04-08

申请号：US13966531

申请日：2013-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Chan Lim ,  Gilheyun Choi ,  Kwangjin Moon ,  Deok-Young Jung ,  Byung-Lyul Park ,  Dosun Lee

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76802 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate.

Abstract translation: 提供一种半导体芯片及其制造方法。 半导体芯片包括具有彼此相对的第一侧和第二侧的基板，以及设置在穿透基板的孔中的贯通电极，其中，由贯通电极包围的开口设置在孔中，其中，开口包括 与基板的第一侧相邻的第一端和与基板的第二侧相邻的第二端。

公开(公告)号：US20140035144A1

公开(公告)日：2014-02-06

申请号：US14047548

申请日：2013-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sukchul Bang ,  Kwangjin Moon ,  Byung Lyul Park ,  Dosun Lee ,  Deok-Young Jung ,  Gilheyun Choi

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate.

Abstract translation: 提供了具有通过电极的半导体器件及其制造方法。 所述方法包括提供包括彼此面对的顶表面和底表面的基板，形成从基板的顶表面延伸到基板的底表面的孔和间隙，围绕孔的间隙并且比孔更浅，填充 所述孔具有绝缘材料，在所述绝缘材料的所述基板的顶表面上形成金属互连线，凹陷所述基板的底表面以暴露所述绝缘材料，去除所述绝缘材料以经由所述孔暴露所述金属互连线 用导电材料填充孔以形成连接到金属互连线的通孔，再次使基板的底表面露出以露出间隙，并在基板的底表面上形成下绝缘层。

公开(公告)号：US20240153851A1

公开(公告)日：2024-05-09

申请号：US18406602

申请日：2024-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEWON HWANG ,  Kwangjin Moon ,  Hojin Lee ,  Hyungjun Jeon

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/48 ,  H01L23/535

CPC classification number: H01L23/485 ,  H01L23/481 ,  H01L23/535 ,  H01L24/29 ,  H01L24/45

Abstract: A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

公开(公告)号：US11887957B2

公开(公告)日：2024-01-30

申请号：US18076529

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jubin Seo ,  Sujeong Park ,  Kwangjin Moon ,  Myungjoo Park

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/13099 ,  H01L2924/014 ,  H01L2924/3651

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, an under-bump pattern on the semiconductor substrate and including a first metal, a bump pattern on the under-bump pattern, and an organic dielectric layer on the semiconductor substrate and in contact with a sidewall of the bump pattern. The bump pattern includes a support pattern in contact with the under-bump pattern and having a first width, and a solder pillar pattern on the support pattern and having a second width. The first width is greater than the second width. The support pattern includes at least one of a solder material and an intermetallic compound (IMC). The intermetallic compound includes the first metal and the solder material.

公开(公告)号：US11810900B2

公开(公告)日：2023-11-07

申请号：US17209801

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk Jung ,  Hyoukyung Cho ,  Jinnam Kim ,  Hyungjun Jeon ,  Kwangjin Moon ,  Hoonjoo Na ,  Hakseung Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/08 ,  H01L2224/08146

Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

公开(公告)号：US11749587B2

公开(公告)日：2023-09-05

申请号：US17855902

申请日：2022-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/481 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having a first surface on which an active region is disposed, and a second surface opposite the first surface, a buried conductive line extending in one direction and having a portion buried in the active region, an insulating portion covering the buried conductive line, a contact structure disposed on the insulating portion and connected to the buried conductive line, a through-hole extending from the second surface to the insulating portion and exposing the buried portion of the buried conductive line, an insulating isolation film disposed on a side surface of the buried conductive line and exposing a bottom surface of the buried portion and a side surface adjacent to the bottom surface, a through-via contacting the bottom surface and the adjacent side surface of the buried conductive line, an insulating liner surrounding the through-via.

公开(公告)号：US11728245B2

公开(公告)日：2023-08-15

申请号：US17316970

申请日：2021-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jubin Seo ,  Kwangjin Moon ,  Kunsang Park ,  Myungjoo Park ,  Sujeong Park ,  Jaewon Hwang

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/53209 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.