公开(公告)号：US10038006B2

公开(公告)日：2018-07-31

申请号：US15269294

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoko Furihata ,  Jixin Yu ,  Hiroyuki Ogawa ,  James Kai ,  Jin Liu ,  Johann Alsmeier

IPC: H01L29/76 ,  H01L29/792 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/02

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US09972640B1

公开(公告)日：2018-05-15

申请号：US15354067

申请日：2016-11-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Murshed Chowdhury ,  Jin Liu ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L29/417 ,  H01L29/51 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02494 ,  H01L21/02587 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/41741 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/518

Abstract: A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

公开(公告)号：US20180122904A1

公开(公告)日：2018-05-03

申请号：US15458200

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuyo Matsumoto ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Hiroyuki Ogawa ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.

公开(公告)号：US09959932B1

公开(公告)日：2018-05-01

申请号：US15437718

申请日：2017-02-21

Applicant: SanDisk Technologies LLC

Inventor： Zhengyi Zhang ,  Yingda Dong ,  James Kai ,  Johann Alsmeier

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/28

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3459

Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.

公开(公告)号：US09917100B2

公开(公告)日：2018-03-13

申请号：US15354116

申请日：2016-11-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tong Zhang ,  Johann Alsmeier ,  James Kai ,  Jin Liu ,  Yanli Zhang

IPC: H01L27/115 ,  H01L23/528 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L28/00

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.

公开(公告)号：US20220229588A1

公开(公告)日：2022-07-21

申请号：US17149867

申请日：2021-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  James Kai ,  Johann Alsmeier ,  Jian Chen

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11582

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.

公开(公告)号：US11380709B2

公开(公告)日：2022-07-05

申请号：US16558712

申请日：2019-09-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yingda Dong ,  James Kai ,  Christopher J. Petti

IPC: H01L21/02 ,  H01L21/00 ,  H01L27/11597 ,  H01L27/1159 ,  G11C11/22 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/786

Abstract: A memory element is provided that includes a portion of a bit line plug, a portion of a source line plug, a portion of a word line, a portion of a vertical semiconductor pillar disposed between the bit line plug, the source line plug and adjacent the word line, and a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line.

公开(公告)号：US11355486B2

公开(公告)日：2022-06-07

申请号：US17062988

申请日：2020-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki Mizutani ,  Masaaki Higashitani ,  James Kai

IPC: H01L25/18 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer.

公开(公告)号：US11195781B2

公开(公告)日：2021-12-07

申请号：US16829667

申请日：2020-03-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Teruo Okina ,  Akio Nishida ,  James Kai

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A pass-through via structure vertically extends through a dielectric material portion that is adjacent to the alternating stack. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A backside bonding pad or bonding wire is formed to be electrically connected to the pass-through via structure.

公开(公告)号：US10727216B1

公开(公告)日：2020-07-28

申请号：US16409593

申请日：2019-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Murshed Chowdhury ,  Koichi Matsuno ,  Johann Alsmeier

IPC: H01L21/76 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.