公开(公告)号：US10181516B2

公开(公告)日：2019-01-15

申请号：US15865795

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Luigi Colombo ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05 ,  H01L29/66 ,  H01L29/45 ,  H01L21/02 ,  H01L29/778 ,  H01L29/51

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function

公开(公告)号：US20180151487A1

公开(公告)日：2018-05-31

申请号：US15361401

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/367 ,  H01L23/373 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/288 ,  H01L21/285 ,  H01L21/324 ,  H01L21/3105

CPC classification number: H01L23/528 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76895 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/53209 ,  H01L23/53276

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

公开(公告)号：US09824769B2

公开(公告)日：2017-11-21

申请号：US15146049

申请日：2016-05-04

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

公开(公告)号：US20160293834A1

公开(公告)日：2016-10-06

申请号：US14676233

申请日：2015-04-01

Applicant: Texas Instruments Incorporated

Inventor： Arup Polley ,  Archana Venugopal ,  Robert Reid Doering ,  Luigi Colombo

IPC: H01L43/10 ,  G01R33/07 ,  H01L43/06

CPC classification number: H01L43/10 ,  G01R33/07 ,  H01L43/065

Abstract: Described examples include graphene Hall sensors, magnetic sensor systems and methods for sensing a magnetic field using an adjustable gate voltage to adapt the Hall sensor magnetic field sensitivity according to a control input for environmental or process compensation and/or real-time adaptation for balancing power consumption and minimum detectable field performance. The graphene Hall sensor gate voltage can be modulated and the sensor output signal can be demodulated to combat flicker or other low frequency noise. Also, graphene Hall sensors can be provided with capacitive coupled contacts for reliable low impedance AC coupling to instrumentation amplifiers or other circuits using integral capacitance.

Abstract translation: 所描述的实例包括石墨烯霍尔传感器，磁传感器系统和用于使用可调节栅极电压感测磁场的方法，以根据用于环境或过程补偿的控制输入和/或用于平衡功率的实时适应来适应霍尔传感器的磁场灵敏度 消耗和最小可检测现场性能。 可以对石墨烯霍尔传感器门电压进行调制，并且传感器输出信号可被解调，以防止闪烁或其他低频噪声。 此外，石墨烯霍尔传感器可以提供电容耦合触点，用于可靠的低阻抗交流耦合到仪表放大器或使用积分电容的其他电路。

公开(公告)号：US09397023B2

公开(公告)日：2016-07-19

申请号：US14499216

申请日：2014-09-28

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Sameer Pendharkar

IPC: H01L23/34 ,  H01L23/373 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/48 ,  H01L21/02

CPC classification number: H01L23/3672 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/76877 ,  H01L23/373 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53276 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2924/00

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract translation: 微电子器件包括在部件的电极上的散热层和散热器层上的金属互连。 散热器层设置在半导体器件的衬底的顶表面之上。 散热器层为100纳米至3微米厚，面内热导率至少为150瓦特/米-2°K，电阻率小于100微欧姆厘米。

公开(公告)号：US20160093551A1

公开(公告)日：2016-03-31

申请号：US14499216

申请日：2014-09-28

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Sameer Pendharkar

IPC: H01L23/373 ,  H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/3672 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/76877 ,  H01L23/373 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53276 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2924/00

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract translation: 微电子器件包括在部件的电极上的散热层和散热器层上的金属互连。 散热器层设置在半导体器件的衬底的顶表面上方。 散热器层为100纳米至3微米厚，面内热导率至少为150瓦特/米-2°K，电阻率小于100微欧姆厘米。

公开(公告)号：US20240363484A1

公开(公告)日：2024-10-31

申请号：US18308411

申请日：2023-04-27

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Jingjing Chen

IPC: H01L23/38 ,  H10N10/01 ,  H10N10/17

CPC classification number: H01L23/38 ,  H10N10/01 ,  H10N10/17

Abstract: An electronic device includes a semiconductor die with first and second sides, a semiconductor layer extending to the first side, an array of unit cells arranged in rows columns, and a conductive reference terminal in the semiconductor layer that laterally surrounds the array, the first and second sides being spaced apart from one another by a thickness distance of 50 μm or less, and the respective unit cells including: a circuit component in the semiconductor layer; a holey semiconductor portion in the semiconductor layer that laterally surrounds the respective circuit component and includes holes that extend from the metallization structure toward the first side; and a conductive control terminal in the semiconductor layer that laterally surrounds the respective holey semiconductor portion, and an adhesive layer extends between the first side of the semiconductor die and a die attach pad.

公开(公告)号：US20240312862A1

公开(公告)日：2024-09-19

申请号：US18674006

申请日：2024-05-24

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/74 ,  H01L21/768 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02

CPC classification number: H01L23/367 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/76895 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L27/0248 ,  H01L21/743 ,  H01L23/3677 ,  H01L2224/48463

Abstract: An integrated circuit includes a semiconductor substrate. The integrated circuit also includes a trench in the semiconductor substrate, the trench including a layer of a nanoparticle material. The integrated circuit further includes an interconnect region above the trench.

公开(公告)号：US20240282812A1

公开(公告)日：2024-08-22

申请号：US18654186

申请日：2024-05-03

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Joseph Maurice Khayat ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/861

CPC classification number: H01L29/0626 ,  H01L29/66113 ,  H01L29/861

Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

公开(公告)号：US20240222527A1

公开(公告)日：2024-07-04

申请号：US18147875

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Natalia Lavrovskaya ,  Archana Venugopal

IPC: H01L29/866 ,  H01L29/06 ,  H01L29/36 ,  H01L29/66

CPC classification number: H01L29/866 ,  H01L29/0646 ,  H01L29/36 ,  H01L29/66106

Abstract: Breakdown diodes and methods of making the same are described. Such a breakdown diode can be fabricated in a semiconductor substrate and have a junction configured to breakdown under a target reverse bias applied across the junctions. The junction is located below the surface of the substrate by a distance suitable for ameliorating mechanical stress impact to the reverse bias breakdown voltage of the junction. Moreover, the junction is located away from an interface causing noise issues.