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    Silicon Dot Formation by Direct Self-Assembly Method for Flash Memory
    43.
    发明申请
    Silicon Dot Formation by Direct Self-Assembly Method for Flash Memory 有权
    通过闪存直接自组装方法形成硅点

    公开(公告)号：US20150054059A1

    公开(公告)日：2015-02-26

    申请号：US13974155

    申请日：2013-08-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ming Chen ,  Cheng-Te Lee ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

    IPC: H01L29/792 ,  H01L29/66

    CPC classification number: H01L21/28273 ,  H01L21/31155 ,  H01L21/32105 ,  H01L21/32139 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements comprising a substantially equal size within a memory cell. A copolymer solution comprising first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material comprising a regular pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first or second polymer species is then removed resulting with a pattern of micro-domains or the polymer matrix with a pattern of holes, which may be utilized as a hard-mask to form a substantially identical pattern of discrete storage elements through an etch, ion implant technique, or a combination thereof.

    Abstract translation: 本公开的一些实施例涉及一种实现在存储器单元内包括基本上相等尺寸的离散存储元件的基本上均匀的图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在基材的表面上，并进行自组装成相分离的材料，该相分离材料包含第二聚合物物质的规则形式的第二聚合物种类的聚合物基质， 第一种聚合物种类。 然后去除第一或第二聚合物物质，其具有微畴图案或具有空穴图案的聚合物基质，其可以用作硬掩模，以通过蚀刻形成基本相同的离散存储元件图案， 离子注入技术或其组合。

    Source/drains in semiconductor devices and methods of forming thereof
    46.
    发明授权
    Source/drains in semiconductor devices and methods of forming thereof 有权

    公开(公告)号：US11824099B2

    公开(公告)日：2023-11-21

    申请号：US16901512

    申请日：2020-06-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Ming Chen ,  Kuei-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/788

    CPC classification number: H01L29/42384 ,  H01L29/785 ,  H01L29/7889

    Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

    Capping structure to reduce dark current in image sensors
    47.
    发明授权
    Capping structure to reduce dark current in image sensors 有权

    公开(公告)号：US11824077B2

    公开(公告)日：2023-11-21

    申请号：US16952384

    申请日：2020-11-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Eugene Chen

    IPC: H01L27/146

    CPC classification number: H01L27/14643 ,  H01L27/14636 ,  H01L27/14685

    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.

    Enhanced trench isolation structure
    48.
    发明授权
    Enhanced trench isolation structure 有权

    公开(公告)号：US11784204B2

    公开(公告)日：2023-10-10

    申请号：US17073553

    申请日：2020-10-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Min-Ying Tsai ,  Cheng-Te Lee ,  Rei-Lin Chu ,  Ching I Li ,  Chung-Yi Yu

    IPC: H01L27/146

    CPC classification number: H01L27/1463 ,  H01L27/14689 ,  H01L27/14698

    Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

    Photolithography alignment process for bonded wafers
    49.
    发明授权
    Photolithography alignment process for bonded wafers 有权

    公开(公告)号：US11362038B2

    公开(公告)日：2022-06-14

    申请号：US17062677

    申请日：2020-10-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yeong-Jyh Lin ,  Ching I Li ,  De-Yang Chiou ,  Sz-Fan Chen ,  Han-Jui Hu ,  Ching-Hung Wang ,  Ru-Liang Lee ,  Chung-Yi Yu

    IPC: H01L23/544 ,  H01L21/027 ,  H01L21/683 ,  G03F1/42 ,  G03F1/70 ,  H01L21/66

    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

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