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    STACKED SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME
    41.
    发明申请
    STACKED SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME 有权

    公开(公告)号：US20210104416A1

    公开(公告)日：2021-04-08

    申请号：US17101608

    申请日：2020-11-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Wei Chen ,  Der-Chyang Yeh ,  Li-Hsien Huang

    IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

    Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

    Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method
    43.
    发明申请
    Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method 审中-公开

    公开(公告)号：US20200294845A1

    公开(公告)日：2020-09-17

    申请号：US16889603

    申请日：2020-06-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Der-Chyang Yeh

    IPC: H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

    Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

    PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF
    44.
    发明申请
    PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF 审中-公开

    公开(公告)号：US20190355687A1

    公开(公告)日：2019-11-21

    申请号：US15980662

    申请日：2018-05-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Hsien Huang ,  An-Jhih Su ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Yueh-Ting Lin ,  Ming-Shih Yeh

    IPC: H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L21/56 ,  H01L23/58

    Abstract: A package structure including a semiconductor die, an insulating encapsulant, a redistribution layer and a plurality of conductive terminals is provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads and a plurality of conductive strips. The conductive pads are disposed on and connected to the plurality of conductive pads, wherein each of the conductive strips is physically connected to at least two conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant and the semiconductor die, wherein the redistribution layer is electrically connected to the plurality of conductive strips. The plurality of conductive terminals is disposed on the redistribution layer.

    FORMING SHALLOW TRENCH FOR DICING AND STRUCTURES THEREOF
    49.
    发明申请
    FORMING SHALLOW TRENCH FOR DICING AND STRUCTURES THEREOF 有权

    公开(公告)号：US20240413102A1

    公开(公告)日：2024-12-12

    申请号：US18462499

    申请日：2023-09-07

    Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

    Inventor： Hung-Pin Chang ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Der-Chyang Yeh

    IPC: H01L23/58 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

    Abstract: A method includes etching a portion of a wafer to form a first trench in a scribe line of the wafer, wherein the scribe line is between a first device die and a second device die of the wafer. After the etching, a top surface of the portion of wafer in the scribe line is underlying and exposed to the first trench, and the first trench is between opposing sidewalls of the wafer. A laser grooving process is then performed to form a second trench extending from the top surface further down into the wafer, and the second trench is laterally between the opposing sidewalls of the wafer. A die-saw process is then performed to saw the wafer. The die-saw process is performed from a bottom of the second trench, and the die-saw process results in the first device die to be separated from the second device die.

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