公开(公告)号：US12062742B2

公开(公告)日：2024-08-13

申请号：US17653659

申请日：2022-03-07

Applicant: Unimicron Technology Corp.

Inventor： Hao-Wei Tseng ,  Chi-Hai Kuo ,  Jeng-Ting Li ,  Ying-Chu Chen ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L33/54 ,  H01L23/00 ,  H01L25/075

CPC classification number: H01L33/54 ,  H01L24/83 ,  H01L25/0753 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29194 ,  H01L2224/32227 ,  H01L2224/83099 ,  H01L2224/83203 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/8389 ,  H01L2924/12041 ,  H01L2933/005

Abstract: A package structure includes a substrate, a plurality of conductive pads, a light-emitting diode, a photo imageable dielectric material, and a black matrix. The substrate includes a top surface. The conductive pads are located on the top surface of the substrate. The light-emitting diode is located on the conductive pads. The photo imageable dielectric material is located between the light-emitting diode and the top surface of the substrate and between the conductive pads. An orthogonal projection of the light-emitting diode on the substrate is overlapped with an orthogonal projection of the photo imageable dielectric material on the substrate. The black matrix is located on the top surface of the substrate and the conductive pads.

公开(公告)号：US20240251504A1

公开(公告)日：2024-07-25

申请号：US18172324

申请日：2023-02-22

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Chin-Sheng Wang ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K3/067 ,  H05K3/4679 ,  H05K2201/09454 ,  H05K2203/0789

Abstract: The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes a line portion, a first insulating layer, and a conductive terminal. The first insulating layer is disposed on the line portion. The conductive terminal is disposed on the first insulating layer and embedded in the first insulating layer to be electrically connected with the line portion. The conductive terminal includes a first portion, a second portion, and a third portion. The first portion protrudes from a surface of the first insulating layer. The second portion is embedded in the first insulating layer and connected to the first portion. The third portion is disposed between the line portion and the second portion. A width of the second portion is greater than a width of the third portion.

公开(公告)号：US11764344B2

公开(公告)日：2023-09-19

申请号：US17209110

申请日：2021-03-22

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang

IPC: H01L33/62 ,  H01L33/06 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L33/54

CPC classification number: H01L33/06 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L33/54 ,  H01L2221/6835 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.

公开(公告)号：US20230240023A1

公开(公告)日：2023-07-27

申请号：US17684421

申请日：2022-03-02

Applicant: Unimicron Technology Corp.

Inventor： Wen-Yu Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Chin-Sheng Wang ,  Guang-Hwa Ma ,  Tzyy-Jang Tseng

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K3/467 ,  H05K1/112 ,  H05K2201/0191

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

公开(公告)号：US20220328387A1

公开(公告)日：2022-10-13

申请号：US17232128

申请日：2021-04-15

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chi-Hai Kuo ,  Chia-Yu Peng ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683

Abstract: A package carrier includes a first redistribution layer having a first upper surface and a first lower surface and including a plurality of first redistribution circuits, a plurality of conductive through holes, a plurality of photoimageable dielectric layers, and a plurality of chip pads and a second redistribution layer disposed on the first upper surface of the first redistribution layer. The second redistribution layer has a second upper surface and a second lower surface aligned with and directly connected to the first upper surface of the first redistribution layer and includes a plurality of second redistribution circuits, a plurality of conductive structures, a plurality of Ajinomoto build-up Film (ABF) layers, and a plurality of solder ball pads. A line width and a line pitch of each of the first redistribution circuits are smaller than a line width and a line pitch of each of the second redistribution circuits.

公开(公告)号：US11445617B2

公开(公告)日：2022-09-13

申请号：US16379816

申请日：2019-04-10

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Cheng-Ta Ko ,  John Hon-Shing Lau ,  Yu-Hua Chen ,  Tzyy-Jang Tseng

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H05K1/14 ,  H01L23/538

Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.

公开(公告)号：US20220271208A1

公开(公告)日：2022-08-25

申请号：US17227391

申请日：2021-04-12

Applicant: Unimicron Technology Corp.

Inventor： Jeng-Ting Li ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H01L33/62 ,  H01L27/15 ,  H01L33/00

Abstract: A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.

公开(公告)号：US11410971B2

公开(公告)日：2022-08-09

申请号：US17098436

申请日：2020-11-15

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Ra-Min Tain

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00

Abstract: A chip package structure includes a substrate, a first chip, a second chip, a bridge, a plurality of first bumps, a plurality of second bumps, a plurality of third bumps and a plurality of solder balls. A first active surface of the first chip and a second active surface of the second chip face a first surface of the substrate. The bridge includes a high-molecular polymer layer and a pad layer located on the high-molecular polymer layer. The first chip is electrically connected to the substrate through the first bumps. The second chip is electrically connected to the substrate through the second bumps. The first chip and the second chip are electrically connected to the pad layer through the third bumps. The first bumps and the second bumps have the same size. The solder balls are disposed on a second surface of the substrate and electrically connected to the substrate.

公开(公告)号：US11366381B2

公开(公告)日：2022-06-21

申请号：US16395244

申请日：2019-04-26

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Shih-Lian Cheng ,  Yu-Hua Chen ,  Cheng-Ta Ko ,  Jui-Jung Chien ,  Wei-Tse Ho

IPC: B32B37/00 ,  G03F1/50 ,  H05K3/06 ,  H05K3/24 ,  H05K3/00 ,  H05K3/10 ,  H05K3/12 ,  H05K3/18 ,  H05K3/42 ,  G03F7/20 ,  G01K7/24 ,  G01K15/00

Abstract: A mask structure and a manufacturing method of the mask structure are provided. The mask structure includes a transparent substrate, a patterned metal layer, and a plurality of microlens structures. The patterned metal layer is disposed on the transparent substrate and exposing a portion of the transparent substrate. The microlens structures are disposed on the transparent substrate exposed by a portion of the patterned metal layer and being in contact with the portion of the patterned metal layer.

公开(公告)号：US11362057B2

公开(公告)日：2022-06-14

申请号：US16687557

申请日：2019-11-18

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Cheng-Ta Ko ,  Ra-Min Tain ,  Tzyy-Jang Tseng

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.