公开(公告)号：US06225221B1

公开(公告)日：2001-05-01

申请号：US09501966

申请日：2000-02-10

申请人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta ,  Chockalingam Ramasamy

发明人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta ,  Chockalingam Ramasamy

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76874 ,  H01L21/76876 ,  H01L2221/1089

摘要： A new method of depositing a copper seed layer in the manufacture of an integrated circuit device has been achieved. The copper seed layer is thin and conformal and well-suited for subsequent electroless plating of copper. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer comprising tantalum, titanium, or tungsten is deposited overlying the dielectric layer to line the vias and trenches. A copper seed layer is deposited overlying the barrier layer by the reaction of CuF2 vapor with the barrier layer, and the integrated circuit is completed.

摘要翻译： 已经实现了在制造集成电路器件中沉积铜种子层的新方法。 铜种子层薄且保形，非常适合随后的铜化学镀。 提供覆盖在半导体衬底上的介电层，其可以包括电介质材料的叠层。 图案化的电介质层形成用于计划的双镶嵌互连的通孔和沟槽。 包含钽，钛或钨的阻挡层沉积在电介质层上，以对通孔和沟槽进行排列。 通过CuF2蒸汽与阻挡层的反应沉积覆盖阻挡层的铜籽晶层，并且集成电路完成。

公开(公告)号：US06132521A

公开(公告)日：2000-10-17

申请号：US467132

申请日：1999-12-20

申请人： Subhash Gupta ,  Simon Chooi ,  Mei Sheng Zhou ,  Paul Ho

发明人： Subhash Gupta ,  Simon Chooi ,  Mei Sheng Zhou ,  Paul Ho

IPC分类号： C11D3/20 ,  C11D3/39 ,  C23G5/032 ,  B08B3/04

CPC分类号： C11D3/2072 ,  C11D3/2003 ,  C11D3/2093 ,  C11D3/3945 ,  C23G5/032 ,  Y10S134/902

摘要： A method of cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware without corroding or damaging the equipment parts and surfaces in the event of wafer breakage and non-wafer breakage is described. A solution includes an alkyldione peroxide, a stabilizing agent, and alcohols is used to oxidize the metal and form soluble complexes which are removed by the cleaning solution. Also, a alkyldione peroxide solution for cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware in the event of wafer breakage and non-wafer breakage is provided.

摘要翻译： 描述了从设备硬件表面清除元素铜，钴或镍的方法，而不会在晶片断裂和非晶片断裂的情况下腐蚀或损坏设备部件和表面。 溶液包括烷基二酮过氧化物，稳定剂，醇用于氧化金属并形成由清洗溶液除去的可溶性络合物。 此外，提供了在晶片断裂和非晶片断裂的情况下从设备硬件的表面清除元素铜，钴或镍的烷基二氧化碳过氧化物溶液。

公开(公告)号：US6063547A

公开(公告)日：2000-05-16

申请号：US94464

申请日：1998-06-11

申请人： Jianhui Ye ,  Mei Sheng Zhou

发明人： Jianhui Ye ,  Mei Sheng Zhou

IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/3213 ,  G03F7/26

CPC分类号： G03F7/091 ,  H01L21/0276 ,  H01L21/32139 ,  H01L21/32137 ,  Y10S430/151

摘要： A method of patterning conductive lines using a bottom anti-reflective coating (BARC) composed of Poly-p-phenylene sulfide (PPS) film 30 formed using a Physical Vapor Deposition (PVD) process. The PPS BARC 30 is easy to remove and has superior planarization. The method comprises:a) forming conductive layer 26 over a semiconductor structure 10;b) forming a Poly-p-phenylene sulfide (PPS) layer 30 over said conductive layer using a Physical Vapor Deposition (PVD) process;c) forming a photoresist pattern 34 over said Poly-p-phenylene sulfide (PPS) layer 30; said Poly-p-phenylene sulfide (PPS) layer acting as a bottom Anti-reflective coating (BARC);d) etching said conductive layer 26 using said photoresist pattern 34 and as a mask forming a conductive pattern;e) removing said photoresist pattern 34;f) removing said Poly-p-phenylene sulfide (PPS) layer by heating and vaporizing said Poly-p-phenylene sulfide (PPS) layer.

摘要翻译： 使用由使用物理气相沉积（PVD）工艺形成的聚对苯硫醚（PPS）膜30组成的底部抗反射涂层（BARC）来图案化导电线的方法。 PPS BARC 30易于去除并具有优异的平面化。 该方法包括：a）在半导体结构10上形成导电层26; b）使用物理气相沉积（PVD）工艺在所述导电层上形成聚对苯硫醚（PPS）层30; c）在所述聚对苯硫醚（PPS）层30上形成光致抗蚀剂图案34; 所述作为底部抗反射涂层（BARC）的聚对苯硫醚（PPS）层; d）使用所述光致抗蚀剂图案34和形成导电图案的掩模蚀刻所述导电层26; e）去除所述光致抗蚀剂图案34; f）通过加热和蒸发所述聚对苯硫醚（PPS）层来除去所述聚对苯硫醚（PPS）层。

公开(公告)号：US5989979A

公开(公告)日：1999-11-23

申请号：US208920

申请日：1998-12-10

申请人： Wen Jun Liu ,  Pei Ching Lee ,  Mei Sheng Zhou

发明人： Wen Jun Liu ,  Pei Ching Lee ,  Mei Sheng Zhou

IPC分类号： H01L21/311 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/31116 ,  H01L21/76202

摘要： A novel anisotropic plasma etching process for forming patterned silicon nitride (Si.sub.3 N.sub.4) layers with improved critical dimension (CD) control while minimizing the Si.sub.3 N.sub.4 footing at the bottom edge of the Si.sub.3 N.sub.4 pattern is achieved. A pad oxide/silicon nitride layer is deposited on a silicon substrate. A patterned photoresist layer is used as an etching mask for etching the silicon nitride layer. By this invention, a chlorine (Cl.sub.2) breakthrough plasma pre-etch forms a protective polymer layer on the sidewalls of the patterned photoresist and removes residue in the open areas prior to etching the Si.sub.3 N.sub.4. The Si.sub.3 N.sub.4 is then aniso-tropically plasma etched using an etch gas containing SF.sub.6. The polymer layer, formed during the Cl.sub.2 pre-etch, reduces the lateral recessing of the photoresist when the Si.sub.3 N.sub.4 is etched, and results in improved patterned Si.sub.3 N.sub.4 profiles with reduced CD bias, and minimizes Si.sub.3 N.sub.4 footings at the bottom edge of the Si.sub.3 N.sub.4 pattern.

摘要翻译： 实现了一种新颖的各向异性等离子体蚀刻工艺，用于在Si 3 N 4图案的底部边缘处最小化Si 3 N 4基脚的同时，形成具有改进的临界尺寸（CD）控制的图案化氮化硅（Si 3 N 4）层。 衬垫氧化物/氮化硅层沉积在硅衬底上。 使用图案化的光致抗蚀剂层作为用于蚀刻氮化硅层的蚀刻掩模。 通过本发明，氯（Cl2）穿透等离子体预蚀刻在图案化光致抗蚀剂的侧壁上形成保护性聚合物层，并且在蚀刻Si 3 N 4之前去除开放区域中的残余物。 然后使用含有SF6的蚀刻气体对Si 3 N 4进行各向异性等离子体蚀刻。 在Cl2预蚀刻期间形成的聚合物层在蚀刻Si 3 N 4时减少了光致抗蚀剂的侧向凹陷，并且导致改善的图案化Si3N4分布，具有降低的CD偏压，并且使Si 3 N 4图案的底部边缘处的Si 3 N 4基底最小化。

公开(公告)号：US5863307A

公开(公告)日：1999-01-26

申请号：US80804

申请日：1998-05-18

申请人： Mei Sheng Zhou ,  Ron-Fu Chu

发明人： Mei Sheng Zhou ,  Ron-Fu Chu

IPC分类号： C09K3/14 ,  H01L21/321 ,  H01L21/768 ,  B24D3/34

CPC分类号： H01L21/7684 ,  C09K3/1472 ,  H01L21/3212

摘要： A Chemical-Mechanical Polish (CMP) planarizing method and a Chemical-Mechanical Polish (CMP) slurry composition for Chemical-Mechanical Polish (CMP) planarizing of copper metal and copper metal alloy layers within integrated circuits. There is first provided a semiconductor substrate having formed upon its surface a patterned substrate layer. Formed within and upon the patterned substrate layer is a blanket copper metal layer or a blanket copper metal alloy layer. The blanket copper metal layer or blanket copper metal alloy layer is then planarized through a Chemical-Mechanical Polish (CMP) planarizing method employing a Chemical-Mechanical Polish (CMP) slurry composition. The Chemical-Mechanical Polish (CMP) slurry composition comprises a non-aqueous coordinating solvent and a halogen radical producing specie.

摘要翻译： 化学机械抛光（CMP）平面化方法和化学机械抛光（CMP）浆料组合物用于集成电路中铜金属和铜金属合金层的化学机械抛光（CMP）平面化。 首先提供了在其表面上形成图案化衬底层的半导体衬底。 形成在图案化衬底层的内部和之上的是铜层金属层或覆盖铜金属合金层。 然后通过使用化学机械抛光（CMP）浆料组合物的化学机械抛光（CMP）平面化方法将橡皮布铜金属层或橡皮布铜金属合金层平坦化。 化学机械抛光（CMP）浆料组合物包含非水配位溶剂和卤素原子产生物。

公开(公告)号：US5747369A

公开(公告)日：1998-05-05

申请号：US782706

申请日：1997-01-13

申请人： Arjun Kumar Kantimahanti ,  Chivukula Subrahmanyam ,  Mei Sheng Zhou

发明人： Arjun Kumar Kantimahanti ,  Chivukula Subrahmanyam ,  Mei Sheng Zhou

IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L21/8242

CPC分类号： H01L28/40 ,  H01L27/0629

摘要： A method is described for forming capacitors in integrated circuits by making the capacitors concurrently with the fabrication of the interconnection wiring levels. A single additional photolithographic step and two depositions are required to form capacitors within each wiring level. A key feature of the invention is the use of an etch-stop to protect the capacitor dielectric during contact or via etching. The storage plates of the capacitor are formed from two successive conductor levels which can include polysilicon levels as well. The process is particularly suited to the manufacture of logic circuits and can be used effectively in MOSFET, bipolar and BiCMOS processes.

摘要翻译： 描述了一种用于在集成电路中形成电容器的方法，其中通过在制造互连线路电平的同时使电容器同时进行。 需要单个附加的光刻步骤和两个沉积以在每个布线层内形成电容器。 本发明的一个关键特征是在接触或通过蚀刻期间使用蚀刻停止来保护电容器电介质。 电容器的存储板由两个连续的导体电平形成，也可以包括多晶硅层。 该过程特别适用于逻辑电路的制造，可以有效地用于MOSFET，双极和BiCMOS工艺。

公开(公告)号：US08754447B2

公开(公告)日：2014-06-17

申请号：US12857543

申请日：2010-08-16

申请人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636

摘要： A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.

摘要翻译： 一种晶体管器件结构，包括：由第一材料形成的衬底部分; 以及源区域，漏极区域和形成在所述衬底中的沟道区域，所述源极和漏极区域包括与所述第一材料不同的多个第二材料岛，所述岛被布置成在所述沟道区域中引起应变 底物。

公开(公告)号：US08716076B2

公开(公告)日：2014-05-06

申请号：US13190805

申请日：2011-07-26

申请人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/338

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US20100019329A1

公开(公告)日：2010-01-28

申请号：US12220792

申请日：2008-07-28

申请人： Debora Chyiu Hyia Poon ,  Alex KH See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Debora Chyiu Hyia Poon ,  Alex KH See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L27/088 ,  H01L21/66 ,  G06F17/50

CPC分类号： H01L27/088 ,  H01L27/0211

摘要： A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

摘要翻译： 制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。 在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。 用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。 如果估计温度低于或高于预定目标温度（或范围），则执行TPC。 可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化 在退火期间。

公开(公告)号：US07060613B2

公开(公告)日：2006-06-13

申请号：US10988692

申请日：2004-11-15

申请人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi

发明人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.