中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

89 records (took 0.022 seconds)

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    41.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150206916A1

    公开(公告)日：2015-07-23

    申请号：US14595870

    申请日：2015-01-13

    Applicant: XINTEC INC.

    Inventor： Po-Han LEE ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chien-Hung LIU

    IPC: H01L27/146 ,  H01L31/0203

    CPC classification number: H01L27/14632 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/1469 ,  H01L2224/11

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A redistribution layer, an insulating layer, and a conductive structure are formed on a second surface of the wafer opposite to the first surface, such that a semiconductor element is formed. The semiconductor element is diced from the insulating layer to the carrier, such that the semiconductor element forms at least one sub-semiconductor element. UV light is used to irradiate the sub-semiconductor element, such that adhesion of the temporary bonding layer is eliminated. The carrier of the sub-semiconductor element is removed.

    Abstract translation: 半导体器件的制造方法包括以下步骤。 临时粘合层用于将载体粘附到晶片的第一表面。 在与第一表面相对的晶片的第二表面上形成再分布层，绝缘层和导电结构，从而形成半导体元件。 半导体元件从绝缘层切割到载体，使得半导体元件形成至少一个子半导体元件。 UV光用于照射次半导体元件，从而消除了临时粘合层的粘附。 子半导体元件的载体被去除。

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    42.
    发明申请
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 有权
    芯片包装及其制造方法

    公开(公告)号：US20140312478A1

    公开(公告)日：2014-10-23

    申请号：US14255883

    申请日：2014-04-17

    Applicant: XINTEC INC.

    Inventor： Chia-Sheng LIN ,  Yen-Shih HO ,  Tsang-Yu LIU

    IPC: H01L23/495 ,  H01L23/00

    CPC classification number: H01L23/4952 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2224/494 ,  H01L2224/8536 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided.

    Abstract translation: 提供芯片封装。 芯片封装包括半导体芯片，隔离层，再分布金属层和接合焊盘。 半导体芯片具有设置在下表面上的第一导电焊盘和对应于第一导电焊盘的第一孔。 第一孔和隔离层从上表面延伸到下表面以暴露第一导电垫。 再分布金属层设置在隔离层上并具有对应于第一导电焊盘的再分布金属线，再分布金属线通过开口连接到第一导电焊盘。 接合焊盘设置在隔离层和半导体芯片的一侧，其中再分布金属线延伸到接合焊盘以将第一导电焊盘电连接到接合焊盘。 还提供了其方法。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    45.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开
    芯片包装及其形成方法

    公开(公告)号：US20130341747A1

    公开(公告)日：2013-12-26

    申请号：US13921999

    申请日：2013-06-19

    Applicant: XINTEC INC.

    Inventor： Po-Shen LIN ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chih-Wei HO ,  Shih-Chin CHEN

    IPC: H01L31/0232 ,  H01L31/02

    CPC classification number: H01L31/0232 ,  H01L23/3114 ,  H01L27/14618 ,  H01L31/02 ,  H01L31/02327 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An embodiment of the invention provides a chip package which includes: a chip including: a semiconductor substrate having a first surface; a device region formed in the semiconductor substrate; and a plurality of micro-lenses on the first surface and the device region; a cover substrate disposed on the chip, wherein the cover substrate is a transparent substrate; a spacer layer disposed between the chip and the cover substrate, wherein the spacer layer, the chip, and the cover substrate collectively surround a cavity in the device region; and at least one main lens on the cover substrate and in the cavity, wherein a width of the main lens is greater than that of each of the micro-lenses.

    Abstract translation: 本发明的实施例提供一种芯片封装，其包括：芯片，包括：具有第一表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 以及在所述第一表面和所述器件区域上的多个微透镜; 设置在所述芯片上的盖基板，其中所述盖基板为透明基板; 设置在所述芯片和所述覆盖基板之间的间隔层，其中所述间隔层，所述芯片和所述覆盖基板一起围绕所述器件区域中的空腔; 以及在所述盖基板上和所述空腔中的至少一个主透镜，其中所述主透镜的宽度大于每个所述微透镜的宽度。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    46.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    芯片包装及其形成方法

    公开(公告)号：US20130328147A1

    公开(公告)日：2013-12-12

    申请号：US13912792

    申请日：2013-06-07

    Applicant: XINTEC INC.

    Inventor： Yen-Shih HO ,  Ying-Nan WEN ,  Tsang-Yu LIU

    IPC: H01L31/02 ,  H01L31/0232

    CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L31/02002 ,  H01L31/0232 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure.

    Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 设置在所述半导体衬底中的器件区域; 设置在所述半导体衬底的第一表面上的电介质层; 布置在所述电介质层中并电连接到所述器件区的导电焊盘结构，设置在所述电介质层上的载体衬底; 以及设置在所述载体基板的底表面中并与所述导电焊盘结构电接触的导电结构。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    48.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20250054849A1

    公开(公告)日：2025-02-13

    申请号：US18779105

    申请日：2024-07-22

    Applicant: Xintec Inc.

    Inventor： Wei-Luen SUEN ,  Po-Jung CHEN ,  Chia-Ming CHENG ,  Po-Shen LIN ,  Jiun-Yen LAI ,  Tsang-Yu LIU ,  Shu-Ming CHANG

    IPC: H01L23/498 ,  H01L21/768 ,  H01L23/15 ,  H01L23/528

    Abstract: A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    49.
    发明公开
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20230369371A1

    公开(公告)日：2023-11-16

    申请号：US17744664

    申请日：2022-05-14

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu LIU ,  Chaung-Lin LAI ,  Shu-Ming CHANG

    IPC: H01L27/146 ,  H01L21/48

    CPC classification number: H01L27/14634 ,  H01L21/481 ,  H01L21/4857 ,  H01L27/14627

    Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.

    MANUFACTURING METHOD OF CHIP PACKAGE
    50.
    发明申请
    MANUFACTURING METHOD OF CHIP PACKAGE 有权

    公开(公告)号：US20210066379A1

    公开(公告)日：2021-03-04

    申请号：US16950810

    申请日：2020-11-17

    Applicant: XINTEC INC.

    Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Po-Han LEE

    IPC: H01L27/146 ,  H01L23/00

    Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

Patent Agency Ranking