公开(公告)号：US08378463B2

公开(公告)日：2013-02-19

申请号：US12974332

申请日：2010-12-21

Applicant: George R. Brandes ,  Robert P. Vaudo ,  Xueping Xu

Inventor： George R. Brandes ,  Robert P. Vaudo ,  Xueping Xu

IPC: H01L29/04

CPC classification number: H01S5/32341 ,  Y10S438/973

Abstract: A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate. In an illustrative implementation, a laser diode is oriented on a GaN substrate wherein the GaN substrate includes a GaN (0001) surface off-cut from the direction predominantly towards either the or the family of directions. For a off-cut substrate, a laser diode cavity may be oriented along the direction parallel to lattice surface steps of the substrate in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For a off-cut substrate, the laser diode cavity may be oriented along the direction orthogonal to lattice surface steps of the substrate in order to provide a cleaved laser facet that is aligned with the surface lattice steps.

Abstract translation: 一种微电子组件，其中半导体器件结构定向地定位在离轴衬底上。 在说明性实施方案中，激光二极管定向在GaN衬底上，其中GaN衬底包括从（0001）方向偏离的GaN（0001）表面，主要朝向<11 20>或<1100> 方向。 对于<11 20>截割衬底，激光二极管空腔可以沿着平行于衬底的晶格表面台阶的<100°方向取向，以便具有与表面晶格步骤正交的切割的激光刻面。 对于<100>切割衬底，激光二极管空腔可以沿着与衬底的晶格表面台阶正交的<100°方向取向，以便提供与表面晶格步骤对准的切割的激光刻面。

公开(公告)号：US08202793B2

公开(公告)日：2012-06-19

申请号：US12855087

申请日：2010-08-12

Applicant: Edward A. Preble ,  Denis Tsvetkov ,  Andrew D. Hanser ,  N. Mark Williams ,  Xueping Xu

Inventor： Edward A. Preble ,  Denis Tsvetkov ,  Andrew D. Hanser ,  N. Mark Williams ,  Xueping Xu

IPC: H01L21/28 ,  H01L21/3205

CPC classification number: H01L21/02694 ,  C30B25/02 ,  C30B25/18 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/02581 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/04 ,  H01L29/0688 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/30 ,  H01L33/32

Abstract: In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps.

Abstract translation: 在制造无夹杂物的均匀半绝缘GaN晶体的方法中，在衬底上沉积外延氮化物层。 3D成核GaN层通过HVPE在基本上3D生长模式下在外延氮化物层上生长，其中成核层的表面基本上被凹坑覆盖，并且凹坑的纵横比基本相同。 在将生长模式从基本上3D生长模式改变为基本上2D生长模式的条件下，通过HVPE在成核层上生长GaN过渡层。 在生长过渡层之后，过渡层的表面基本上是无凹坑的。 通过HVPE在过渡层上生长体GaN层。 在生长本体层之后，本体层的表面是光滑的并且基本上无凹坑。 在至少一个上述GaN生长步骤期间，GaN掺杂有过渡金属。

公开(公告)号：US07777217B2

公开(公告)日：2010-08-17

申请号：US11606633

申请日：2006-11-30

Applicant: Edward A. Preble ,  Denis Tsvetkov ,  Andrew D. Hanser ,  N. Mark Williams ,  Xueping Xu

Inventor： Edward A. Preble ,  Denis Tsvetkov ,  Andrew D. Hanser ,  N. Mark Williams ,  Xueping Xu

IPC: H01L31/00

CPC classification number: H01L21/02694 ,  C30B25/02 ,  C30B25/18 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/02581 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/04 ,  H01L29/0688 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/30 ,  H01L33/32

Abstract: In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps.

Abstract translation: 在制造无夹杂物的均匀半绝缘GaN晶体的方法中，在衬底上沉积外延氮化物层。 3D成核GaN层通过HVPE在基本上3D生长模式下在外延氮化物层上生长，其中成核层的表面基本上被凹坑覆盖，并且凹坑的纵横比基本相同。 在将生长模式从基本上3D生长模式改变为基本上2D生长模式的条件下，通过HVPE在成核层上生长GaN过渡层。 在生长过渡层之后，过渡层的表面基本上是无凹坑的。 通过HVPE在过渡层上生长体GaN层。 在生长本体层之后，本体层的表面是光滑的并且基本上无凹坑。 在至少一个上述GaN生长步骤期间，GaN掺杂有过渡金属。

公开(公告)号：US20090099016A1

公开(公告)日：2009-04-16

申请号：US12158318

申请日：2006-12-19

Applicant: J. Donald Carruthers ,  Xueping Xu ,  Luping Wang

Inventor： J. Donald Carruthers ,  Xueping Xu ,  Luping Wang

IPC: D01F9/12 ,  C23C16/02 ,  C01B31/08 ,  B01J8/00

CPC classification number: B01J20/205 ,  B01J20/20 ,  B01J21/185 ,  B01J23/74 ,  B01J23/881 ,  B01J23/882 ,  B01J23/883 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/162 ,  C01B2202/02 ,  C01B2202/08 ,  C01B2202/36 ,  Y02P20/582

Abstract: A method and apparatus for manufacture of carbon nanotubes, in which a substrate is contacted with a hydrocarbonaceous feedstock containing a catalytically effective metal to deposit the feedstock on the substrate, followed by oxidation of the deposited feedstock to remove hydrocarbonaceous and carbonaceous components from the substrate, while retaining the catalytically effective metal thereon, and contacting of the substrate having retained catalytically effective metal thereon with a carbon source material to grow carbon nanotubes on the substrate. The manufacture can be carried out with a petroleum feedstock such as an oil refining atmospheric tower residue, to produce carbon nanotubes in high volume at low cost. Also disclosed is a composite including porous material having single-walled carbon nanotubes in pores thereof.

Abstract translation: 一种用于制造碳纳米管的方法和装置，其中将基底与含有催化有效金属的含烃原料接触以将原料沉积在基底上，随后氧化沉积的原料以从基底中除去含碳和碳质的组分， 同时在其上保留催化有效的金属，并且将具有保留的催化有效金属的基材与碳源材料接触以在基材上生长碳纳米管。 可以用石油原料如炼油大气塔渣进行制造，以低成本大量生产碳纳米管。 还公开了一种复合材料，其包括在其孔中具有单壁碳纳米管的多孔材料。

公开(公告)号：US07323256B2

公开(公告)日：2008-01-29

申请号：US10712351

申请日：2003-11-13

Applicant: Xueping Xu ,  Robert P. Vaudo

Inventor： Xueping Xu ,  Robert P. Vaudo

IPC: B32B9/00

CPC classification number: C30B29/406 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/0254 ,  H01L31/184 ,  H01L33/0075 ,  Y10T428/21 ,  Y10T428/265

Abstract: Large area, uniformly low dislocation density single crystal III-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm2, a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm−2, and a dislocation density standard deviation ratio of less than 25%. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Abstract translation: 大面积均匀低位错密度的单晶III-V族氮化物材料，例如，具有大于15cm 2的大面积的氮化镓，至少1mm的厚度，不是的平均位错密度 超过5E5cm -2，位错密度标准偏差比小于25％。 这样的材料可以通过以下工艺在基底上形成，该方法包括：（i）在凹陷生长条件下在衬底上生长III-V族氮化物材料的第一相，例如在III的生长表面的至少50％上形成凹坑 -V氮化物材料，其中生长表面上的凹坑密度为生长表面的至少10 2个/厘米2，和（ii）生长的第二阶段 在填埋条件下的III-V族氮化物材料。

公开(公告)号：US20080003786A1

公开(公告)日：2008-01-03

申请号：US11856222

申请日：2007-09-17

Applicant: Xueping Xu ,  Robert Vaudo

Inventor： Xueping Xu ,  Robert Vaudo

IPC: H01L21/20 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: C30B29/406 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/0254 ,  H01L31/184 ,  H01L33/0075 ,  Y10T428/21 ,  Y10T428/265

Abstract: Large area, uniformly low dislocation density single crystal Ill-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm2, a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm−2, and a dislocation density standard deviation ratio of less than 25%, and methods of forming same, are disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the Ill-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Abstract translation: 大面积均匀低位错密度的单晶III-V族氮化物材料，例如具有大于15cm 2的大面积的氮化镓，至少1mm的厚度，不是的平均位错密度 超过5E5cm -2，位错密度标准偏差比小于25％，以及其形成方法。 这样的材料可以通过以下工艺在基底上形成，该方法包括：（i）在凹陷生长条件下在衬底上生长III-V族氮化物材料的第一阶段，例如在III的生长表面的至少50％上形成凹坑 -V氮化物材料，其中生长表面上的凹坑密度为生长表面的至少10 2个/厘米2，和（ii）生长的第二阶段 在填埋条件下的III-V族氮化物材料。

公开(公告)号：US07090554B1

公开(公告)日：2006-08-15

申请号：US10603415

申请日：2003-06-24

Applicant: Roger W. Barton ,  Kollengode S. Narayanan ,  Bob L. Mackey ,  John M. Macaulay ,  George B. Hopple ,  Donald R. Schropp, Jr. ,  Michael J. Nystrom ,  Sudhakar Gopalakrishnan ,  Shiyou Pei ,  Xueping Xu

Inventor： Roger W. Barton ,  Kollengode S. Narayanan ,  Bob L. Mackey ,  John M. Macaulay ,  George B. Hopple ,  Donald R. Schropp, Jr. ,  Michael J. Nystrom ,  Sudhakar Gopalakrishnan ,  Shiyou Pei ,  Xueping Xu

IPC: H01J9/00

CPC classification number: H01J9/242 ,  H01J29/028 ,  H01J29/864 ,  H01J31/127 ,  H01J2329/863 ,  H01J2329/8635 ,  H01J2329/864 ,  H01J2329/8645 ,  H01J2329/866

Abstract: A flat-panel display is fabricated by a process in which a spacer (24) having a rough face (54 or 56) is positioned between a pair of plate structure (20 and 22). When electrons strike the spacer, the roughness in the spacer's face causes the number of secondary electrons that escape the spacer to be reduced, thereby alleviating positive charge buildup on the spacer. As a result, the image produced by the display is improved. The spacer facial roughness can be achieved in various ways such as providing suitable depressions (60, 62, 64, 66, 70, 74, or 80) or/and protuberances (82, 84, 88, and 92) along the spacer's face.

Abstract translation: 平板显示器是通过一种方法制造的，其中具有粗糙面（54或56）的间隔物（24）位于一对板结构（20和22）之间。 当电子撞击间隔物时，间隔物表面的粗糙度导致逸出间隔物的二次电子数量减少，从而减轻间隔物上的正电荷积累。 结果，改善了由显示器产生的图像。 间隔件面部粗糙度可以以各种方式实现，例如沿着间隔件的表面提供合适的凹陷（60,62,64,66,70,74或80）或/和突起（82,84,88和92）。

公开(公告)号：US20050009310A1

公开(公告)日：2005-01-13

申请号：US10618024

申请日：2003-07-11

Applicant: Robert Vaudo ,  Xueping Xu ,  George Brandes

Inventor： Robert Vaudo ,  Xueping Xu ,  George Brandes

IPC: H01L21/205 ,  H01L29/20 ,  H01L29/207 ,  H01L21/337 ,  H01L21/265 ,  H01L29/06 ,  H01L31/153

CPC classification number: H01L29/207 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02581 ,  H01L21/0262 ,  H01L29/2003

Abstract: Large-area, single crystal semi-insulating gallium nitride that is usefully employed to form substrates for fabricating GaN devices for electronic and/or optoelectronic applications. The large-area, semi-insulating gallium nitride is readily formed by doping the growing gallium nitride material during growth thereof with a deep acceptor dopant species, e.g., Mn, Fe, Co, Ni, Cu, etc., to compensate donor species in the gallium nitride, and impart semi-insulating character to the gallium nitride.

Abstract translation: 大面积的单晶半绝缘氮化镓，其有效地用于形成用于制造用于电子和/或光电应用的GaN器件的衬底。 大面积半绝缘氮化镓容易通过在其生长期间掺杂生长的氮化镓材料与深受主掺杂物质（例如Mn，Fe，Co，Ni，Cu等）来形成，以补偿在 氮化镓，并赋予氮化镓半绝缘特性。

公开(公告)号：US06680489B1

公开(公告)日：2004-01-20

申请号：US09557165

申请日：2000-04-25

Applicant: George R. Brandes ,  Chris S. Christos ,  Xueping Xu

Inventor： George R. Brandes ,  Chris S. Christos ,  Xueping Xu

IPC: H01L310312

CPC classification number: H01L28/20 ,  H01J1/3042 ,  H01J2201/30403 ,  H01J2201/319 ,  H01J2329/00 ,  H01L31/03765 ,  Y02E10/548

Abstract: Amorphous silicon carbide thin film structures, including: protective coatings for windows in infrared process stream monitoring systems and sensor domes, heated windows, electromagnetic interference shielding members and integrated micromachined sensors; high-temperature sensors and circuits; and diffusion barrier layers in VLSI circuits. The amorphous silicon carbide thin film structures are readily formed, e.g., by sputtering at low temperatures.

Abstract translation: 无定形碳化硅薄膜结构，包括：红外线工艺流监测系统和传感器圆顶中的窗户保护涂层，加热窗，电磁干扰屏蔽构件和集成微机械传感器; 高温传感器和电路; 和VLSI电路中的扩散阻挡层。 非晶碳化硅薄膜结构容易形成，例如通过在低温下溅射。

公开(公告)号：US06379210B2

公开(公告)日：2002-04-30

申请号：US09727023

申请日：2000-11-29

Applicant: Xueping Xu ,  George R. Brandes ,  Christopher J. Spindt ,  Colin D. Stanners ,  John M. Macaulay

Inventor： Xueping Xu ,  George R. Brandes ,  Christopher J. Spindt ,  Colin D. Stanners ,  John M. Macaulay

IPC: H01J902

CPC classification number: H01J1/3042 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2329/00

Abstract: A cathode structure suitable for a flat panel display is provided with coated emitters. The emitters are formed with material, typically nickel, capable of growing to a high aspect ratio. These emitters are then coated with carbon containing material for improving the chemical robustness and reducing the work function. One coating process is a DC plasma deposition process in which acetylene is pumped through a DC plasma reactor to create a DC plasma for coating the cathode structure. An alternative coating process is to electrically deposit raw carbon-based material onto the surface of the emitters, and subsequently reduce the raw carbon-based material to the carbon containing material. Work function of coated emitters is typically reduced by about 0.8 to 1.0 eV.

Abstract translation: 适用于平板显示器的阴极结构设置有涂覆的发射器。 发射体由能够生长到高纵横比的材料（通常为镍）形成。 然后，这些发射体涂覆有含碳材料，以改善化学稳定性并降低功函数。 一个涂覆工艺是DC等离子体沉积工艺，其中将乙炔泵送通过DC等离子体反应器以产生用于涂覆阴极结构的DC等离子体。 另一种涂覆方法是将原始碳基材料电沉积到发射体的表面上，随后将原始的碳基材料还原成含碳材料。 涂覆发射体的功函数通常降低约0.8至1.0eV。