公开(公告)号：US20230411284A1

公开(公告)日：2023-12-21

申请号：US18230182

申请日：2023-08-04

申请人： NANYA TECHNOLOGY CORPORATION

发明人： KUO-HUI SU

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/535

CPC分类号： H01L23/528 ,  H01L23/5329 ,  H01L23/535 ,  H01L21/76895 ,  H01L21/7682 ,  H01L21/76885

摘要： The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.

公开(公告)号：US20230411209A1

公开(公告)日：2023-12-21

申请号：US17842548

申请日：2022-06-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hung-Yu YEN ,  Keng-Chu LIN

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/7682 ,  H01L23/5226 ,  H01L21/76826 ,  H01L21/76802

摘要： A method for manufacturing a semiconductor device includes: forming a patterned mask on a patterned structure disposed on a substrate, such that a first mask portion and a second mask portion of the patterned mask are disposed on a first interconnect feature and a second interconnect feature of the patterned structure, respectively; and subjecting the patterned mask to a plasma treatment process such that the first and second mask portions are deformed to form a capping portion to cap a recess disposed between the first and second interconnect features so as to form an air gap.

公开(公告)号：US11848253B2

公开(公告)日：2023-12-19

申请号：US17521805

申请日：2021-11-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Ching-Pin Hsu ,  Chih-Jung Wang ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Purakh Raj Verma

IPC分类号： H01L23/482 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L23/4821 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/7682 ,  H01L21/76243 ,  H01L23/485

摘要： A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.

公开(公告)号：US11842966B2

公开(公告)日：2023-12-12

申请号：US17355613

申请日：2021-06-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai ,  Hsin-Yen Huang ,  Chia-Tien Wu

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/532

CPC分类号： H01L23/5384 ,  H01L21/486 ,  H01L21/7682 ,  H01L21/76802 ,  H01L23/5329 ,  H01L23/5386

摘要： The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.

公开(公告)号：US11837546B2

公开(公告)日：2023-12-05

申请号：US17714428

申请日：2022-04-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Hao Liao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5329 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5226

摘要： The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.

公开(公告)号：US20230387005A1

公开(公告)日：2023-11-30

申请号：US18201995

申请日：2023-05-25

申请人： Samsung Electronics Co., Ltd.

发明人： Junhyeok Ahn ,  Jinkuk Bae

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/528 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/7682 ,  H01L23/53266

摘要： A semiconductor device includes a first contact structure connected to the lower structure, a first conductive wiring connected to the first contact structure, a first etch-stop layer and an interlayer insulating layer sequentially provided on the first conductive wiring, a second contact structure passing through the first etch-stop layer, provided in the interlayer insulating layer, and connected to the first conductive wiring, a second conductive wiring provided on the second contact structure and provided in the interlayer insulating layer, a barrier layer including a first barrier portion on a bottom surface of the second contact structure, a second etch-stop layer provided on a top surface of the second conductive wiring and a top surface of the interlayer insulating layer, and an air gap between the barrier layer and the extension portion.

公开(公告)号：US20230386901A1

公开(公告)日：2023-11-30

申请号：US18230338

申请日：2023-08-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ting-Ya LO ,  Cheng-Chin LEE ,  Shao-Kuan LEE ,  Chi-Lin TENG ,  Hsin-Yen HUANG ,  Hsiaokang CHANG ,  Shau-Lin SHUE

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/7682 ,  H01L23/5226 ,  H01L21/76846 ,  H01L21/76837 ,  H01L21/76832

摘要： A method for forming an interconnect structure includes forming a first conductive layer over a dielectric layer, forming one or more openings in the first conductive layer to expose portions of dielectric surface of the dielectric layer and conductive surfaces of the first conductive layer, wherein the one or more openings separates the first conductive layer into one or more portions. The method includes forming a capping layer on exposed portions of the dielectric surface of the dielectric layer and conductive surface of the first conductive layer, forming a sacrificial layer in the one or more openings, recessing the sacrificial layer, forming a support layer on the recessed sacrificial layer in each of the one or more openings, removing the sacrificial layer to form an air gap in each of the one or more openings, forming a dielectric fill on the support layer, replacing the first conductive layer in the one or more openings with a second conductive layer, selectively forming a two-dimensional (2D) material layer on the second conductive layer, forming a first etch stop layer on the dielectric fill and the support layer, forming a second etch stop layer on the first etch stop layer and the 2D material layer, forming a dielectric material on the second etch stop layer, forming a contact opening through the dielectric material, the second etch stop layer, and the 2D material layer to expose a top surface of the second conductive layer, and forming a first conductive feature in the contact opening.

公开(公告)号：US11830769B2

公开(公告)日：2023-11-28

申请号：US17869337

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Hao Chang ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L21/768 ,  H01L21/76 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/06

CPC分类号： H01L21/7682 ,  H01L21/76 ,  H01L21/76834 ,  H01L23/5286 ,  H01L23/53295 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02172 ,  H01L21/02274 ,  H01L29/0673

摘要： A semiconductor structure includes first and second source/drain (S/D) features, one or more semiconductor channel layers connecting the first and second S/D features, a gate structure engaging the one or more semiconductor channel layers, a metal wiring layer at a backside of the semiconductor structure, an S/D contact electrically connecting the first S/D feature to the metal wiring layer, and a seal layer between the metal wiring layer and the gate structure. The seal layer is spaced away from the gate structure by an air gap therebetween.

公开(公告)号：US20230377953A1

公开(公告)日：2023-11-23

申请号：US18248562

申请日：2021-10-01

申请人： Tokyo Electron Limited

发明人： Hiroki MURAKAMI

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  C23C16/40 ,  C23C16/34 ,  C23C16/52 ,  H01J37/32

CPC分类号： H01L21/7682 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/31055 ,  H01L21/31138 ,  H01L21/31116 ,  H01L21/76831 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02211 ,  C23C16/402 ,  C23C16/345 ,  C23C16/52 ,  H01J37/32449 ,  H01J2237/3321 ,  H01J2237/3341

摘要： A substrate processing method includes: preparing a substrate having a recess and a first film embedded in the recess; and removing the first film by etching while forming a second film so as to cover the recess from which the first film was removed by supplying a processing gas to the substrate, the processing gas including a gas contributing to film formation and a gas contributing to the etching.

公开(公告)号：US11804439B2

公开(公告)日：2023-10-31

申请号：US17745509

申请日：2022-05-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Gulbagh Singh ,  Kun-Tsang Chuang ,  Po-Jen Wang

IPC分类号： H01L23/535 ,  H01L21/74 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/482 ,  H01L27/12

CPC分类号： H01L23/535 ,  H01L21/743 ,  H01L21/7682 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/4821 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/53223 ,  H01L23/53295 ,  H01L27/1203

摘要： The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.