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    Bipolar transistor and a method for manufacturing the same
    41.
    发明申请
    Bipolar transistor and a method for manufacturing the same 失效
    双极晶体管及其制造方法

    公开(公告)号：US20030218184A1

    公开(公告)日：2003-11-27

    申请号：US10394663

    申请日：2003-03-24

    Inventor： Masaki Yanagisawa

    IPC: H01L031/0328 ,  H01L021/8249

    CPC classification number: H01L29/66318 ,  H01L21/76838 ,  H01L29/045 ,  H01L29/0821 ,  H01L29/7371

    Abstract: A hetero-bipolar transistor according to the present invention enhances reliability that relates to the breaking of wiring metal. The transistor comprises a semiconductor substrate, a sub-collector layer formed on a (100) surface of the substrate, a collector mesa formed on the sub-collector layer, and an emitter contact layer. The transistor further includes a collector electrode and wiring metal connected to the collector electrode. The edge of the sub-collector layer forms a step S, the angle of which is in obtuse relative to the substrate. Therefore, the wiring metal traversing the step S bends in obtuse angle at the step S, thus reducing the breaking of the wiring metal.

    Abstract translation: 根据本发明的异双极晶体管提高了与布线金属的断裂有关的可靠性。 晶体管包括半导体衬底，形成在衬底的（100）表面上的子集电极层，形成在子集电极层上的集电极台面和发射极接触层。 晶体管还包括集电极和连接到集电极的布线金属。 子集电极层的边缘形成了相对于衬底钝角的台阶S。 因此，穿过步骤S的布线金属在步骤S处以钝角弯曲，从而减少了布线金属的断裂。

    Array substrate used for a display device and a method of making the same
    42.
    发明申请
    Array substrate used for a display device and a method of making the same 有权
    用于显示装置的阵列基板及其制造方法

    公开(公告)号：US20030209726A1

    公开(公告)日：2003-11-13

    申请号：US10395100

    申请日：2003-03-25

    Applicant: TFPD Corporation

    Inventor： Hirotaka Shigeno

    IPC: H01L031/0328

    CPC classification number: H01L27/12 ,  G02F1/133555 ,  H01L27/1244 ,  H01L27/1248

    Abstract: A TFT array substrate used for a display device and a method of making the same are disclosed. A optically transparent thick resin insulation film 5 is formed on a base substrate and an upper contact hole 51 is perforated through the optically transparent thick resin insulation film 5. A lower contact hole 41 perforated through a gate insulation film 15 and patterning of an ITO film to make a transparent pixel electrode are then collectively carried out under a photoresist pattern 8. Where the photoresist pattern 8 is provided after making the ITO film, an aperture 81 is perforated closer to the center of the upper contact hole 51 at an end portion of a connecting line 14a for a pad and is smaller in diameter by a side etching size plus a margin than the upper contact hole. Subsequently, following three-etching steps are carried out: (1) patterning of the ITO film along the photoresist pattern 8, (2) the lower contact hole 41 is made by using buffered hydrofluoric acid solution, and (3) an nulleavesnull portion 6a of the ITO films is removed.

    Abstract translation: 公开了用于显示装置的TFT阵列基板及其制造方法。 光学透明的厚树脂绝缘膜5形成在基底基板上，并且上部接触孔51穿过光学透明的厚树脂绝缘膜5.穿过栅绝缘膜15的下接触孔41和ITO膜的图形化 制造透明像素电极然后在光致抗蚀剂图案8下共同地进行。在制造ITO膜之后设置光致抗蚀剂图案8的情况下，在上接触孔51的中心处开孔81在端接部分 用于焊盘的连接线14a，并且通过侧蚀刻尺寸加上比上接触孔的边缘更小的直径。 随后，进行三蚀刻步骤：（1）沿着光致抗蚀剂图案8图案化ITO膜，（2）通过使用缓冲氢氟酸溶液制造下接触孔41，（3）“檐” 除去ITO膜的部分6a。

    Multi-level shielded multi-conductor interconnect bus for MEMS
    44.
    发明申请
    Multi-level shielded multi-conductor interconnect bus for MEMS 有权
    用于MEMS的多层屏蔽多导体互连总线

    公开(公告)号：US20030201470A1

    公开(公告)日：2003-10-30

    申请号：US10426433

    申请日：2003-04-30

    Inventor： Stephen Matthew Barnes ,  Samuel Lee Miller ,  Murray Steven Rodgers

    IPC: H01L031/0328

    CPC classification number: H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A multi-level shielded multi-conductor interconnect bus for use in interconnecting MEM devices with control signal sources and a method of fabricating a multi-level shielded multi-conductor interconnect bus are disclosed. In one embodiment, a multi-level shielded interconnect bus (410A) formed on a substrate (20) includes first and second level electrically conductive lines (42, 92) arranged in sets of one, two or more conductive lines between first and second level electrically conductive shield walls (46, 66, 96). The first and second level electrically conductive lines (42, 92) are surrounded by various layers of dielectric material (30, 50, 80, 100). A first level electrically conductive shield (78) overlies the first level electrically conductive lines (42) and shield walls (46, 66). A second level electrically conductive shield (112) overlies the second level electrically conductive lines (92) and shield walls (96).

    Abstract translation: 公开了一种用于将MEM器件与控制信号源互连的多电平屏蔽多导体互连总线和制造多电平屏蔽多导体互连总线的方法。 在一个实施例中，形成在衬底（20）上的多级屏蔽互连总线（410A）包括第一和第二级导电线（42,92），其布置成在第一和第二级之间的一条，两条或更多条导线 导电屏蔽壁（46,66,96）。 第一和第二级导电线（42,92）被各种介电材料层（30,50,80,100）包围。 第一级导电屏蔽（78）覆盖在第一级导电线（42）和屏蔽壁（46,66）之间。 第二级导电屏蔽（112）覆盖在第二级导电线（92）和屏蔽壁（96）上。

    Strained fin fets structure and method
    45.
    发明申请
    Strained fin fets structure and method 有权
    应变鳍结构和方法

    公开(公告)号：US20030201458A1

    公开(公告)日：2003-10-30

    申请号：US10439886

    申请日：2003-05-16

    Inventor： William F. Clark ,  David M. Fried ,  Louis D. Lanzerotti ,  Edward J. Nowak

    IPC: H01L031/0328

    CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

    Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

    Abstract translation: 一种在绝缘体上包括绝缘体和硅结构的晶体管的方法和结构。 硅结构包括中心部分和从中心部分的端部延伸的翅片。 第一栅极位于硅结构的中心部分的第一侧上。 应变产生层可以位于硅结构的中心部分的第一栅极和第一侧之间，第二栅极位于硅结构的中心部分的第二侧上。

    TAB tape for semiconductor package
    46.
    发明申请
    TAB tape for semiconductor package 有权
    TAB胶带用于半导体封装

    公开(公告)号：US20030197200A1

    公开(公告)日：2003-10-23

    申请号：US10359080

    申请日：2003-02-06

    Inventor： Dong Han Kim ,  Hyoung Ho Kim

    IPC: H01L031/0328

    CPC classification number: H01L22/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/15173 ,  H01L2924/00

    Abstract: A TAB tape for a semiconductor package is provided. The TAB tape provides number of test pad configuration for reducing the area of the test pad area on a TAB tape to increases the number of packages that may be prepared from a length of TAB tape. The TAB tape comprises a base film having a chip mounting area for mounting at least one semiconductor device and a wiring pattern formed on the base film with test pads formed at the ends of the output terminal patterns. A predetermined number of the test pads are arranged in rows form a group wherein the number of rows is less than the number of test pads in the group. Groups of the test pads are consecutively arranged across the TAB tape to provide the number of test pads necessary for testing the semiconductor device(s).

    Abstract translation: 提供了一种用于半导体封装的TAB带。 TAB磁带提供了用于减小TAB磁带上的测试焊盘区域的面积的测试焊盘配置的数量，以增加可从一段TAB磁带制备的封装的数量。 TAB带包括具有用于安装至少一个半导体器件的芯片安装区域和形成在基底膜上的布线图案的基底膜，其具有形成在输出端子图案的端部处的测试焊盘。 预定数量的测试焊盘以行的形式排列，其中行数小于组中的测试焊盘的数量。 测试焊盘的组被连续布置在TAB带上，以提供测试半导体器件所需的测试焊盘的数量。

    ELECTRICAL-OPTICAL PACKAGE WITH CAPACITOR DC SHUNTS AND ASSOCIATED METHODS
    48.
    发明申请
    ELECTRICAL-OPTICAL PACKAGE WITH CAPACITOR DC SHUNTS AND ASSOCIATED METHODS 有权
    具有电容直流电的电光学封装及相关方法

    公开(公告)号：US20030183893A1

    公开(公告)日：2003-10-02

    申请号：US10109314

    申请日：2002-03-28

    Applicant: Intel Corporation

    Inventor： Yuan-Liang Li

    IPC: H01L029/06 ,  H01L031/0328 ,  H01L031/0336

    CPC classification number: G02B6/43 ,  G02B6/4232 ,  H01L31/12 ,  H01L2224/16225

    Abstract: An optical-electrical (OE) package includes a substrate electrically coupled to a motherboard via one or more capacitor DC shunts (CDCSs). In one embodiment, the substrate includes an IC chip electrically coupled to a first set of contact-receiving members on an upper surface of the substrate. The substrate also includes a light-emitting package and a photodetector package electrically coupled to respective second and third sets of contact-receiving members on the substrate lower surface. The substrate has internal wiring that electrically interconnects the IC chip, the light-emitting package and the photodetector array. The light-emitting package and the photodetector array are optically coupled to respective first and second waveguide arrays formed in or on the motherboard. The CDCSs mitigate noise generated by the IC chip by serving as a local current source.

    Abstract translation: 光电（OE）封装包括经由一个或多个电容器DC分路（CDCS）电耦合到母板的基板。 在一个实施例中，衬底包括电连接到衬底的上表面上的第一组接触件的IC芯片。 衬底还包括发光封装和光电检测器封装，电耦合到衬底下表面上相应的第二组和第三组接触件。 衬底具有将IC芯片，发光封装和光电检测器阵列电互连的内部布线。 发光封装和光电检测器阵列光学耦合到形成在母板中或母板上的相应的第一和第二波导阵列。 CDCS通过作为本地电流源来减轻由IC芯片产生的噪声。

    Hetero-junction bipolar transistor
    50.
    发明申请
    Hetero-junction bipolar transistor 失效
    异质结双极晶体管

    公开(公告)号：US20030183846A1

    公开(公告)日：2003-10-02

    申请号：US10347694

    申请日：2003-01-22

    Applicant: FUJITSU QUANTUM DEVICES LIMITED

    Inventor： Hiroyuki Oguri

    IPC: H01L031/0328 ,  H01L031/0336 ,  H01L031/072

    CPC classification number: H01L29/66318 ,  H01L29/0817 ,  H01L29/7371

    Abstract: A hetero-junction bipolar transistor includes a collector layer, a base layer and an emitter layer, an emitter electrode containing Au being provided for the emitter layer, and an Au-diffusion barrier layer of InP or InGaP interposed between the emitter electrode and the base layer.

    Abstract translation: 异质结双极晶体管包括集电极层，基极层和发射极层，为发射极层提供包含Au的发射极，以及置于发射极和基极之间的InP或InGaP的Au扩散阻挡层 层。

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