公开(公告)号：US20240282351A1

公开(公告)日：2024-08-22

申请号：US18195322

申请日：2023-05-09

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  HOA VU ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  NGHIA LE ,  DUC NGUYEN ,  HIEN PHAM

IPC: G11C7/16 ,  G11C7/12 ,  G11C7/14

CPC classification number: G11C7/16 ,  G11C7/12 ,  G11C7/14

Abstract: In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising: a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and an analog-to-digital converter to convert one or more of the first voltage and the second voltage into a set of output bits.

公开(公告)号：US20240274187A1

公开(公告)日：2024-08-15

申请号：US18645018

申请日：2024-04-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO ,  MARK REITEN

IPC: G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/423 ,  H01L29/788 ,  H10B41/30

CPC classification number: G11C11/54 ,  G06N3/045 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7883 ,  H10B41/30

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell columns, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

公开(公告)号：US12061976B2

公开(公告)日：2024-08-13

申请号：US17181656

申请日：2021-02-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06N3/065 ,  G06F3/06 ,  G06F17/16 ,  G06N3/08 ,  G11C27/02

CPC classification number: G06N3/065 ,  G06F3/0688 ,  G06F17/16 ,  G06N3/08 ,  G11C27/02

Abstract: Numerous output circuits are disclosed for an analog neural memory system for a deep learning neural network. In one embodiment, an adaptable neuron circuit receives output current from a neuron and converts it into a voltage. In another embodiment, a current sample and hold circuit samples an input current and generates an output current. In another embodiment, a voltage sample and hold circuit samples an input voltage and generates an output voltage.

公开(公告)号：US12057170B2

公开(公告)日：2024-08-06

申请号：US18139908

申请日：2023-04-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Stephen Trinh ,  Thuan Vu ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/10 ,  G06N3/065 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C16/10 ,  G06N3/065 ,  G11C11/5628 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/3459

Abstract: In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.

公开(公告)号：US12033692B2

公开(公告)日：2024-07-09

申请号：US18124334

申请日：2023-03-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/423 ,  H01L29/788 ,  H10B41/30

CPC classification number: G11C11/54 ,  G06N3/045 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7883 ,  H10B41/30

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

公开(公告)号：US12014793B2

公开(公告)日：2024-06-18

申请号：US17858185

申请日：2022-07-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C29/50

CPC classification number: G11C29/50016 ,  G11C16/14 ,  G11C16/26 ,  G11C16/349 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M1, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking, and screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M1.

公开(公告)号：US20240112736A1

公开(公告)日：2024-04-04

申请号：US18536186

申请日：2023-12-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Nhan Do ,  Mark Reiten

IPC: G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.

公开(公告)号：US20240104357A1

公开(公告)日：2024-03-28

申请号：US18077686

申请日：2022-12-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stephen Trinh ,  Stanley Hong ,  Thuan Vu ,  Nghia Le ,  Hien Pham

IPC: G06N3/048

CPC classification number: G06N3/048

Abstract: Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling signals in response to the address; a first plurality of registers to store, sequentially, activation data in response to the plurality of row enabling signals; and a second plurality of registers to store, in parallel, activation data received from the first plurality of registers.

公开(公告)号：US20240095511A1

公开(公告)日：2024-03-21

申请号：US18522153

申请日：2023-11-28

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Vipin TIWARI ,  Mark REITEN ,  Nhan DO

IPC: G06N3/065 ,  G06F3/06 ,  G06F17/16 ,  G06N3/08 ,  G11C27/02

CPC classification number: G06N3/065 ,  G06F3/0688 ,  G06F17/16 ,  G06N3/08 ,  G11C27/02

Abstract: In one example, a circuit comprises an input transistor comprising a first terminal, a second terminal coupled to ground, and a gate; a capacitor comprising a first terminal and a second terminal; an output transistor comprising a first terminal providing an output current, a second terminal coupled to ground, and a gate; a first switch; and a second switch; wherein in a first mode, the first switch is closed and couples an input current to the first terminal of the input transistor and the gate of the input transistor and the second switch is closed and couples the first terminal of the input transistor to the first terminal of the capacitor and the gate of the output transistor, and in a second mode, the first switch is open and the second switch is open and the capacitor discharges into the gate of the output transistor.

公开(公告)号：US20240095508A1

公开(公告)日：2024-03-21

申请号：US18520277

申请日：2023-11-27

Applicant: Silicon Storage Technology, inc.

Inventor： HIEU VAN TRAN ,  STANLEY HONG ,  AHN LY ,  THUAN VU ,  HIEN PHAM ,  KHA NGUYEN ,  HAN TRAN

IPC: G06N3/065 ,  G06F17/16 ,  G06N3/04

CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/04

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns; a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and a word line driver coupled to the plurality of word lines, the word line driver comprising a plurality of select transistors coupled to a common control line and the plurality of word lines, and a plurality of bias transistors coupled to the plurality of select transistors and capable of providing a bias voltage to a single select transistor in the plurality of select transistors or to all of plurality of select transistors in response to control signals.