公开(公告)号：US08493687B2

公开(公告)日：2013-07-23

申请号：US12964313

申请日：2010-12-09

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Atsushi Iijima

IPC分类号： G11B5/127

CPC分类号： G11B5/3163 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/315

摘要： A magnetic head includes a shield, and first and second return path sections. The shield has an end face that is located in a medium facing surface to wrap around an end face of a main pole. The shield includes a bottom shield, two side shields, and a top shield. The first return path section includes a yoke layer, and first and second coupling layers that magnetically couple the bottom shield and the yoke layer to each other. The first coupling layer is magnetically connected to the bottom shield. The second coupling layer magnetically couples the first coupling layer to the yoke layer. No end faces of the second coupling layer are exposed in the medium facing surface. The second return path section magnetically couples the top shield and the main pole to each other.

摘要翻译： 磁头包括屏蔽，以及第一和第二返回路径部分。 屏蔽件具有位于面向介质的表面中以围绕主极端面的端面。 屏蔽包括底部屏蔽，两个侧面屏蔽和顶部屏蔽。 第一返回路径部分包括轭层，以及使底屏蔽和轭层彼此磁耦合的第一和第二耦合层。 第一耦合层磁性地连接到底部屏蔽。 第二耦合层将第一耦合层磁耦合到轭层。 没有第二耦合层的端面在面向介质的表面中露出。 第二返回路径部分将顶部屏蔽和主极彼此磁耦合。

公开(公告)号：US08482105B2

公开(公告)日：2013-07-09

申请号：US12656458

申请日：2010-01-29

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L21/50 ,  H01L21/768 ,  H01L23/28 ,  H01L23/498 ,  H01L2224/16145

摘要： A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode with a portion thereof arranged within the unit region. Further, the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof.

摘要翻译： 半导体基板具有沿划线形成的多个槽部。 半导体衬底包括：与所述多个沟槽部分中的至少任一个接触的单位区域; 以及布线电极，其部分布置在单元区域内。 此外，多个槽部具有宽口结构，其宽度在宽度方面比包括底部的槽下部宽的部分形成在其入口处。

公开(公告)号：US08462482B2

公开(公告)日：2013-06-11

申请号：US12363188

申请日：2009-01-30

申请人： Yoshitaka Sasaki ,  Atsushi Iijima ,  Hiroshi Ikejima

发明人： Yoshitaka Sasaki ,  Atsushi Iijima ,  Hiroshi Ikejima

IPC分类号： H01G4/06

CPC分类号： H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  Y10T29/435

摘要： In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out.

摘要翻译： 在根据本发明的陶瓷电容器中，在基板上垂直于基板的表面布置有叉指对的内部电极，并且将陶瓷电介质部件填充到该一对内部电极之间的间隙中。 因此，在形成陶瓷电介质部件之前和/或之后，内部电极的尺寸基本上不会发生变化，从而可以保持在内部电极时形成的尺寸。 根据该陶瓷电容器，由于可以容易地控制内部电极尺寸，因此也可以容易地进行内部电极间隔的尺寸控制。

公开(公告)号：US08446696B2

公开(公告)日：2013-05-21

申请号：US12588551

申请日：2009-10-19

申请人： Xianwen Feng ,  Jugang Zhang ,  Tan Tian

发明人： Xianwen Feng ,  Jugang Zhang ,  Tan Tian

IPC分类号： G11B5/55 ,  G11B21/08

CPC分类号： G11B5/486

摘要： A suspension for a head gimbal assembly comprises a flexure having a flexure having a tail with a plurality of electrical traces and a plurality of bonding terminals adapted for connecting with a flexible printed circuit formed thereon. Each of the bonding terminals comprises a connecting pad and a hole formed at one end of the connecting pad for electrically and mechanically connecting the connecting pad to the flexible printed circuit by bonding material. And the connecting pad has a bonding portion adjacent to the hole and an exposed portion for testing. The invention also discloses a head gimbal assembly and a disk drive unit with the same.

摘要翻译： 用于头部万向架组件的悬架包括挠曲件，其具有具有多个电迹线的尾部的弯曲部和适于与形成在其上的柔性印刷电路连接的多个接合端子。 每个接合端子包括连接焊盘和形成在连接焊盘的一端的孔，用于通过接合材料将连接焊盘电连接到机械地连接到柔性印刷电路。 并且连接焊盘具有与孔相邻的接合部分和用于测试的暴露部分。 本发明还公开了一种磁头万向架组件和具有该磁头驱动单元的磁盘驱动单元。

公开(公告)号：US08446693B2

公开(公告)日：2013-05-21

申请号：US11866334

申请日：2007-10-02

申请人： Ming Gao Yao ,  Masashi Shiraishi ,  Yi Ru Xie

发明人： Ming Gao Yao ,  Masashi Shiraishi ,  Yi Ru Xie

IPC分类号： G11B5/60

CPC分类号： G11B5/6082 ,  Y10T29/49032 ,  Y10T29/49041

摘要： A system and method are disclosed for a subambient pressure air bearing slider utilizing negative pressure grooves. In one embodiment, a groove extends from a slider's leading edge, splits, and terminates in two locations at the slider's trailing edge. In one embodiment, a groove is provided in a slider's compression pad near the trailing edge of the slider.

摘要翻译： 公开了一种利用负压槽的低压空气轴承滑块的系统和方法。 在一个实施例中，凹槽从滑块的前缘延伸，分裂并终止于滑块的后缘处的两个位置。 在一个实施例中，在滑块的靠近滑块的后缘的压缩垫中设置凹槽。

公开(公告)号：US08415793B2

公开(公告)日：2013-04-09

申请号：US12929385

申请日：2011-01-20

申请人： Yoshitaka Sasaki ,  Tatsushi Shimizu

发明人： Yoshitaka Sasaki ,  Tatsushi Shimizu

IPC分类号： H01L23/50

CPC分类号： H01L23/49805 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

摘要： A wafer for electronic component packages is used for manufacturing a plurality of electronic component packages, each of the plurality of electronic component packages including: a base incorporating a plurality of external connecting terminals; and at least one electronic component chip bonded to the base and electrically connected to the plurality of external connecting terminals. The wafer has a plurality of sets of external connecting terminals corresponding to the plurality of electronic component packages, a retainer for retaining the plurality of sets of external connecting terminals, and a coupling portion for coupling the plurality of sets of external connecting terminals to one another. The wafer includes a plurality of pre-base portions that will each be subjected to bonding of the at least one electronic component chip thereto and will be subjected to separation from one another later so that each of them will thereby become the base.

摘要翻译： 用于电子部件封装的晶片用于制造多个电子部件封装，所述多个电子部件封装中的每一个包括：包含多个外部连接端子的基座; 以及至少一个电子部件芯片，其结合到所述基座并电连接到所述多个外部连接端子。 晶片具有多个对应于多个电子部件封装的外部连接端子组，用于保持多组外部连接端子的保持器和用于将多组外部连接端子彼此连接的联接部 。 晶片包括多个预基部，每个前基部将各自经受至少一个电子部件芯片的接合，并且将稍后彼此分离，从而它们将因此变为基部。

公开(公告)号：US20130075935A1

公开(公告)日：2013-03-28

申请号：US13240048

申请日：2011-09-22

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L23/52

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L24/06 ,  H01L24/24 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03011 ,  H01L2224/0346 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1064 ,  H01L2924/07802 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/0105

摘要： A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other.

摘要翻译： 复合分层芯片封装包括堆叠的第一和第二子封装。 每个子包包括主体和接线。 主体包括：具有顶表面和底表面的主要部分; 第一端子设置在主要部件的顶表面上; 以及设置在主要部分的底表面上的第二端子。 第一端子和第二端子电连接到布线。 第一子包和第二子包以不同于参考相对位置关系的特定相对位置关系彼此排列。

公开(公告)号：US20130050877A1

公开(公告)日：2013-02-28

申请号：US13222035

申请日：2011-08-31

申请人： Shen kuang Sidney CHOU ,  Chi hung YUEN ,  Yan bin WANG ,  Li ping PENG ,  Lu XIAO

发明人： Shen kuang Sidney CHOU ,  Chi hung YUEN ,  Yan bin WANG ,  Li ping PENG ,  Lu XIAO

IPC分类号： G11B5/40 ,  G11B5/60

CPC分类号： G11B5/10 ,  G11B5/3106 ,  G11B5/40 ,  G11B5/4826 ,  G11B5/4853 ,  G11B5/6005 ,  G11B5/6082

摘要： A slider includes a substrate having a trailing edge, a leading edge opposite the trailing edge, and an air bearing surface connecting the trailing edge with the leading edge; a read/write transducer formed at the trailing edge; and a coat layer attached on the trailing edge and covering on the read/write transducer. The slider further includes a protection layer for shielding the read/write transducer thereby preventing the read/write transducer from damaging during a laser soldering process. The present invention can prevent the read/write transducer from damaging during the laser bonding process and, in turn improve the reading and writing performance of the slider. The invention also discloses an HGA and a disk drive unit.

摘要翻译： 滑块包括具有后缘，与后缘相对的前缘的衬底和将后缘与前缘连接的空气支承表面; 形成在后缘的读/写换能器; 并且附着在后缘上并覆盖读/写换能器的涂层。 滑块还包括用于屏蔽读/写换能器的保护层，从而防止读/写换能器在激光焊接过程中损坏。 本发明可以防止读/写换能器在激光焊接过程中受损，从而提高滑块的读写性能。 本发明还公开了一种HGA和盘驱动单元。

公开(公告)号：US08362602B2

公开(公告)日：2013-01-29

申请号：US12852767

申请日：2010-08-09

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC分类号： H01L23/02

CPC分类号： H01L25/50 ,  H01L23/5382 ,  H01L24/01 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/07802 ,  H01L2924/00

摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other.

摘要翻译： 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括多个层部分; 多个第一端子，其设置在所述主体部的上表面并与所述布线连接; 以及多个第二端子，其设置在所述主体部的底面并与所述布线连接。 每个层部分包括半导体芯片。 多个第二端子被定位成在垂直于主体顶表面的方向上与多个第一端子重叠。 经由导线电连接的多对第一和第二端子包括定位为不彼此重叠的多对第一端子和第二端子。

公开(公告)号：US20120313260A1

公开(公告)日：2012-12-13

申请号：US13156941

申请日：2011-06-09

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/48 ,  H01L21/30

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

摘要： A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括：具有顶表面和底表面并且包括彼此堆叠的三个或更多个层部分的主要部分; 多个第一端子，设置在所述主要部件的顶表面上; 以及设置在主要部分的底表面上的多个第二端子。 每个层部分包括具有第一和第二表面的半导体芯片和电连接到布线的多个电极。 多个电极设置在半导体芯片的第一表面的一侧。 位于最靠近主要部分的顶表面的第一层部分和最靠近主要部分的底表面的第二层部分被布置成使得它们各自的半导体芯片的第二表面朝向彼此。 多个第一端子通过使用第一层部分的多个电极形成。 多个第二端子通过使用第二层部分的多个电极形成。