公开(公告)号：US20110127486A1

公开(公告)日：2011-06-02

申请号：US12929610

申请日：2011-02-03

申请人： Sumio Hosaka ,  Hayato Sone ,  Masaki Yoshimaru ,  Takashi Ono ,  Mayumi Nakasato

发明人： Sumio Hosaka ,  Hayato Sone ,  Masaki Yoshimaru ,  Takashi Ono ,  Mayumi Nakasato

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2436 ,  H01L29/685 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/148

摘要： A phase-change channel transistor includes a first electrode; a second electrode; a memory layer provided between the first and second electrodes; and a third electrode provided for the memory layer with an insulating film interposed therebetween, wherein the memory layer includes at least a first layer formed from a phase-change material which is stable in either an amorphous phase or a crystalline phase at room temperature and a second layer formed from a resistive material, and wherein the resistance value of the second layer is smaller than the resistance value of the first layer in the amorphous phase, but is larger than the resistance value of the first layer in the crystalline phase.

摘要翻译： 相变沟道晶体管包括第一电极; 第二电极; 设置在第一和第二电极之间的存储层; 以及设置在所述存储层中的绝缘膜的第三电极，其中所述存储层至少包括由在室温下在非晶相或结晶相中稳定的相变材料形成的第一层，以及 由电阻材料形成的第二层，并且其中所述第二层的电阻值小于所述第一层在所述非晶相中的电阻值，但大于所述第一层在所述结晶相中的电阻值。

公开(公告)号：US07892975B2

公开(公告)日：2011-02-22

申请号：US11688684

申请日：2007-03-20

申请人： Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

发明人： Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

IPC分类号： H01L21/441

CPC分类号： H01L21/76879 ,  C23C18/1216 ,  C23C18/1279 ,  C23C18/1283 ,  H01L21/288 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electric conductor, the metal compound including a metal serving as a main component of the electric conductor, and dissolving at least part of the metal compound in the supercritical fluid, selectively introducing the metal compound dissolved in the supercritical fluid into the recess in contact with a surface of the processing target, and coagulating in the recess the metal compound introduced into the recess to precipitate the metal from the metal compound, and coagulating the metal precipitated in the recess, thereby providing the electric conductor in the recess.

摘要翻译： 一种用于选择性地形成电导体的方法，所述方法包括在包括超临界流体的气氛中设置处理对象和金属化合物，所述处理对象在其上形成有至少一个用于提供导电体的凹部，所述金属化合物包括金属 作为电导体的主要成分，将至少一部分金属化合物溶解在超临界流体中，选择性地将溶解在超临界流体中的金属化合物导入到与加工对象的表面接触的凹部中， 所述金属化合物引入所述凹部中以将所述金属从所述金属化合物中沉淀出来并将所述金属凝结在所述凹部中沉淀，由此在所述凹部中提供所述电导体。

公开(公告)号：US07869548B2

公开(公告)日：2011-01-11

申请号：US11051630

申请日：2005-01-27

申请人： Takahide Terada ,  Shingo Yoshizumi ,  Tadahiro Kuroda

发明人： Takahide Terada ,  Shingo Yoshizumi ,  Tadahiro Kuroda

IPC分类号： H04L27/06

CPC分类号： H04B1/71637

摘要： In an ultra-wideband receiver for receiving discontinuous pulse signals and for demodulating the receive signals, an amplifier amplifies signals received, and a demodulator demodulates the amplified signals. A controller controls the demodulator and the amplifier based on the signals demodulated by the demodulator. The controller sends a signal to the amplifier to activate the amplifier only when the signals are received in order to decrease the power consumption in the amplifier. Further, the demodulator demodulates the amplified signals by generating a plurality of single pulses as template pulses, multiplies the amplified signals with the plurality of signal pulses, and integrates the multiplied signals to obtain demodulated data.

摘要翻译： 在用于接收不连续脉冲信号和解调接收信号的超宽带接收机中，放大器放大接收到的信号，并且解调器解调放大的信号。 控制器根据由解调器解调的信号控制解调器和放大器。 控制器向放大器发送一个信号，只有在收到信号才能激活放大器，以降低放大器的功耗。 此外，解调器通过产生多个单个脉冲作为模板脉冲来解调放大的信号，将放大的信号与多个信号脉冲相乘，并且对乘法信号进行积分以获得解调数据。

公开(公告)号：US07834786B2

公开(公告)日：2010-11-16

申请号：US12436289

申请日：2009-05-06

申请人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/10

CPC分类号： H03M1/1009 ,  G11C27/026 ,  H03M1/1215

摘要： A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

摘要翻译： 提供了一种采样保持电路，用于并行化的多个低速流水线A / D转换器的时间交错A / D转换装置。 采样保持电路包括采样电容器和采样保持放大器，并且通过使用开关电容器来操作来采样和保持输入信号。 采样保持电路的加法电路通过将产生的具有与采样时钟信号和采样时钟信号的频率相同的频率的斜坡校准信号和基于采样时钟信号的预定斜率输入到输入信号中，将斜坡校准信号添加到 采样保持放大器经由具有小于采样电容器的电容的校准电容器。

公开(公告)号：US07702979B2

公开(公告)日：2010-04-20

申请号：US11397899

申请日：2006-04-05

申请人： Masayuki Arai ,  Kazuhiko Iwasaki ,  Satoshi Fukumoto ,  Takeshi Shoda ,  Junichi Nishimoto

发明人： Masayuki Arai ,  Kazuhiko Iwasaki ,  Satoshi Fukumoto ,  Takeshi Shoda ,  Junichi Nishimoto

IPC分类号： G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318536

摘要： An object of the invention is to drastically reduce the area overhead in a semiconductor integrated circuit incorporating a test configuration that uses a partially rotational scan circuit. To achieve this, in the semiconductor integrated circuit incorporating the test configuration that comprises a combinational circuit (3) and a scan chain (2) constructed by connecting a plurality of scan flip-flops (5) in a chain, the scan chain (2) is divided into a plurality of sub scan-chains (20a to 20n) each of which has a partially rotational scan (PRS) function and a test response compaction (MISR) function. By performing a scan test in a plurality of steps while changing the combination of the sub scan-chains to be set as PRS and the sub scan-chains to be set as MISR, the test can be performed without having to provide a test response compactor separately from the scan chain, and thus the area overhead can be reduced.

摘要翻译： 本发明的一个目的是大大减少包含使用部分旋转扫描电路的测试配置的半导体集成电路中的面积开销。 为了实现这一点，在包括组合电路（3）和通过连接多个扫描触发器（5）构成的扫描链（2）的测试配置的半导体集成电路中，扫描链（2） ）被分成多个子扫描链（20a至20n），每个子扫描链具有部分旋转扫描（PRS）功能和测试响应压缩（MISR）功能。 通过在将要设置为PRS的子扫描链和将被设置为MISR的副扫描链的组合改变的同时执行多个步骤中的扫描测试，可以执行测试而不必提供测试响应压缩器 与扫描链分开，因此可以减少面积开销。

公开(公告)号：US20090325328A1

公开(公告)日：2009-12-31

申请号：US12585119

申请日：2009-09-03

申请人： Seiji Samukawa ,  Satoshi Nishikawa ,  Shingo Kadomura

发明人： Seiji Samukawa ,  Satoshi Nishikawa ,  Shingo Kadomura

IPC分类号： H01L21/66

CPC分类号： H01J37/32935 ,  G01R31/1263 ,  H01J2237/0206

摘要： A plasma processing method is provided. The method includes providing photon detection sensors for measuring an ultraviolet-light-induced current around circumferential portions of a wafer stage within a plasma chamber. The method also includes providing a semiconductor wafer on the wafer stage and performing plasma processing so as to form an insulating layer the semiconductor wafer or etch an insulating layer formed on the semiconductor wafer.

摘要翻译： 提供等离子体处理方法。 该方法包括提供光子检测传感器，用于测量等离子体室内的晶片台周围的紫外光感应电流。 该方法还包括在晶片台上提供半导体晶片并执行等离子体处理，以便形成半导体晶片的绝缘层或蚀刻形成在半导体晶片上的绝缘层。

公开(公告)号：US07612700B2

公开(公告)日：2009-11-03

申请号：US12139754

申请日：2008-06-16

申请人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

发明人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

IPC分类号： H03M1/38

CPC分类号： H03M1/002 ,  H03M1/0695 ,  H03M1/164 ,  H03M1/361 ,  H03M1/442

摘要： In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.

摘要翻译： 在A / D转换电路中，A / D变换电路部分包括A / D变换电路部分，并且以流水线形式A / D转换采样保持信号， 用于将输入信号转换为数字信号的A / D转换器电路，以及用于将数字信号转换为模拟控制信号进行D / A转换的乘法D / A转换器电路，以及通过采样，保持和/ 使用基于模拟控制信号的采样电容放大输入信号。 预充电电路在采样之前对采样电容器进行预充电，以便根据数字输入获得预定的输出值，以输出特性基本上适合于每个A / D转换器电路部分的输入到输出特性，该输出特性呈现对应于 输入信号到每个A / D转换器电路部分。

公开(公告)号：US07609100B2

公开(公告)日：2009-10-27

申请号：US11826271

申请日：2007-07-13

申请人： Makoto Nagata

发明人： Makoto Nagata

IPC分类号： H03L7/06 ,  H03K3/00

CPC分类号： G01R31/2884 ,  G01R31/31924

摘要： An on-chip signal waveform measurement apparatus mounted on an IC chip measures signal waveforms at detection points on the IC chip. A reference voltage generator successively generates reference voltages different from each other based on a predetermined timing signal, and Signal probing front-end circuits are mounted to correspond to the detection points, respectively, and each buffer-amplifies a voltage at each detection point, compares the buffer-amplified voltage with each reference voltage, and digitizes a comparison result into a binary digital output signal. A multiplexer time-division-multiplexes the binary digital output signals from the signal probing front-end circuits. A data processing unit calculates a judgment output probability for a detected voltage at each detection point detected by the respective signal probing front-end circuits, by counting a number of times of a predetermined binary value of the multiplexed binary digital output signal.

摘要翻译： 安装在IC芯片上的片上信号波形测量装置测量IC芯片上的检测点处的信号波形。 参考电压发生器基于预定的定时信号连续产生彼此不同的参考电压，并且分别安装信号探测前端电路以对应于检测点，并且每个缓冲放大每个检测点处的电压， 具有每个参考电压的缓冲放大电压，并将比较结果数字化为二进制数字输出信号。 复用器对来自信号探测前端电路的二进制数字输出信号进行时分复用。 数据处理单元通过对多路复用的二进制数字输出信号的预定二进制值的次数进行计数来计算由各个信号探测前端电路检测的每个检测点处的检测电压的判断输出概率。

公开(公告)号：US20090236747A1

公开(公告)日：2009-09-24

申请号：US12382624

申请日：2009-03-19

申请人： Junichi Koike ,  Yoshito Fujii ,  Jun Iijima ,  Noriyoshi Shimizu ,  Kazuyoshi Maekawa ,  Koji Arita ,  Ryotaro Yagi ,  Masaki Yoshimaru

发明人： Junichi Koike ,  Yoshito Fujii ,  Jun Iijima ,  Noriyoshi Shimizu ,  Kazuyoshi Maekawa ,  Koji Arita ,  Ryotaro Yagi ,  Masaki Yoshimaru

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76853 ,  H01L21/288 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76861 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilevel interconnect structure in a semiconductor device comprises a first insulating layer (2) formed on a semiconductor wafer (1), a Cu interconnect layer (4) formed on the first insulating layer (2), a second insulating layer (6) formed on the Cu interconnect layer (4), and a metal oxide layer (5) formed at an interface between the Cu interconnect layer (4) and the second insulating layer (6). The metal oxide layer (5) is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer (4) and then heat-treating the plated layer in an oxidizing atmosphere.

摘要翻译： 半导体器件中的多层互连结构包括形成在半导体晶片（1）上的第一绝缘层（2），形成在第一绝缘层（2）上的Cu互连层（4），形成第二绝缘层（6） 在Cu互连层（4）上形成的金属氧化物层（5）形成在Cu互连层（4）与第二绝缘层（6）之间的界面处。 通过在Cu互连层（4）上浸渍诸如Sn或Zn的金属，然后在氧化气氛中对镀层进行热处理，形成金属氧化物层（5）。

公开(公告)号：US20080206949A1

公开(公告)日：2008-08-28

申请号：US11845615

申请日：2007-08-27

申请人： Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

发明人： Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

IPC分类号： H01L21/44 ,  B05C11/00

CPC分类号： H01L21/283 ,  C23C18/06 ,  C23C18/08 ,  H01L21/76879

摘要： A conductor forming apparatus includes a reaction container having housed therein a processing target on a surface of which a recess in which a conductor is to be provided is formed, and a process for providing the conductor in the recess being carried out inside the container after a supercritical fluid dissolved with a metal compound is supplied into the container, a supply device which supplies the fluid from an outside to the inside of the container, and a discharge device which discharges the fluid that is not submitted for the process from the inside to the outside of the container, wherein while an amount of the fluid in the container is adjusted by continuously supplying the fluid into the container by the supply device and continuously discharging the fluid that is not submitted for the process to the outside of the container by the discharge device.

摘要翻译： 导体形成装置包括反应容器，其中容纳有处理目标，其表面上形成有要在其中设置导体的凹部，并且在凹部中提供导体的过程在容器内部被执行 将与金属化合物一起溶解的超临界流体供给到容器内，从外部向容器内部供给流体的供给装置以及将未从内部排出的流体从内部排出到 在容器外部，其中通过由供应装置连续地将流体供给到容器中并且通过排出物将不被处理的流体连续排出到容器的外部来调节容器中的流体的量 设备。