公开(公告)号：US20060046399A1

公开(公告)日：2006-03-02

申请号：US10925566

申请日：2004-08-25

Applicant: Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Mark Bohr ,  Anand Murthy

Inventor： Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Mark Bohr ,  Anand Murthy

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.

Abstract translation: 栅极结构可以用作掩模以形成源区和漏区。 然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。 在将沟槽形成衬底的过程中，去除源极漏极区的一部分。 然后用外延材料填充衬底，并在其上形成新的栅极结构。 结果，可以实现更突然的源极漏极结。

公开(公告)号：US06998686B2

公开(公告)日：2006-02-14

申请号：US10230944

申请日：2002-08-28

Applicant: Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

Inventor： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

IPC: H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.

Abstract translation: 描述了具有多层栅电极结构的CMOS晶体管结构和制造方法。 栅电极结构具有三层金属栅电极和多晶硅层。 第一金属层用作阻挡层以防止第二金属层与下面的电介质反应。 第二金属层用于设定栅电极结构的功函数。 第三金属层用作阻挡第二金属层与多晶硅层反应的屏障。

公开(公告)号：US20060017098A1

公开(公告)日：2006-01-26

申请号：US10896124

申请日：2004-07-20

Applicant: Mark Doczy ,  Jack Kavalieros ,  Matthew Metz ,  Justin Brask ,  Suman Datta ,  Robert Chau

Inventor： Mark Doczy ,  Jack Kavalieros ,  Matthew Metz ,  Justin Brask ,  Suman Datta ,  Robert Chau

IPC: H01L29/76

CPC classification number: H01L21/28194 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor device is described that comprises a gate dielectric and a metal gate electrode that comprises an aluminide.

公开(公告)号：US20050285213A1

公开(公告)日：2005-12-29

申请号：US10877836

申请日：2004-06-24

Applicant: Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau

Inventor： Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28247 ,  H01L21/26586 ,  H01L21/28238 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.

Abstract translation: 在金属栅极更换工艺中，杯状栅极金属氧化物电介质可以具有可暴露于硅离子注入的垂直部分。 作为注入的结果，可以减小垂直部分的介电常数，减少边缘电容。

公开(公告)号：US06974733B2

公开(公告)日：2005-12-13

申请号：US10463080

申请日：2003-06-16

Applicant: Boyan Boyanov ,  Brian Doyle ,  Jack Kavalieros ,  Anand Murthy ,  Robert Chau

Inventor： Boyan Boyanov ,  Brian Doyle ,  Jack Kavalieros ,  Anand Murthy ,  Robert Chau

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/338

CPC classification number: H01L29/7842 ,  H01L29/1054 ,  H01L29/66666 ,  H01L29/7827

Abstract: There is disclosed an apparatus including a straining substrate, a device over the substrate including a channel, wherein the straining substrate strains the device in a direction substantially perpendicular to a direction of current flow in the channel.

Abstract translation: 公开了一种装置，包括应变基片，包括通道的衬底上的器件，其中应变衬底沿着基本上垂直于沟道中的电流方向的方向施加器件。

公开(公告)号：US20050263483A1

公开(公告)日：2005-12-01

申请号：US11196034

申请日：2005-08-03

Applicant: Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Robert Chau

Inventor： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Robert Chau

IPC: B44C1/22 ,  C09K13/00 ,  C09K13/06 ,  H01L21/302 ,  H01L21/3213

CPC classification number: H01L21/32134 ,  C09K13/06

Abstract: Semiconductor integrated circuit structures, such as stacks containing metal layers, may be etched with a modified viscosity etchant. An increased viscosity etchant, for example, may reduce undercutting when a metal film is being etched.

Abstract translation: 半导体集成电路结构，例如包含金属层的堆叠，可以用修改的粘度蚀刻剂进行蚀刻。 例如，当蚀刻金属膜时，增加的粘度蚀刻剂可以减少底切。

公开(公告)号：US06970373B2

公开(公告)日：2005-11-29

申请号：US10679124

申请日：2003-10-02

Applicant: Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott A. Hareland

Inventor： Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott A. Hareland

IPC: G11C11/412 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/423 ,  H01L29/786 ,  G11C11/00

CPC classification number: G11C11/412 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

Abstract translation: 本发明是包括两个存取装置的CMOS SRAM单元，每个存取装置由具有单个鳍片的三栅晶体管组成; 两个上拉装置，每个上拉装置由具有单个鳍片的三栅极晶体管组成; 和两个下拉器件，每个下拉器件由具有多个鳍片的三栅晶体管组成。 还提供了一种用于制造包括双鳍三栅极晶体管的CMOS SRAM单元的方法。

公开(公告)号：US20050250258A1

公开(公告)日：2005-11-10

申请号：US10839077

申请日：2004-05-04

Applicant: Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

Inventor： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC: H01L21/8238 ,  H01L21/335

CPC classification number: H01L21/823842

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a masking layer on a first part of the high-k gate dielectric layer. After forming a first metal layer on the masking layer and on an exposed second part of the high-k gate dielectric layer, the masking layer is removed. A second metal layer is then formed on the first metal layer and on the first part of the high-k gate dielectric layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成高k栅极电介质层，并在高k栅极电介质层的第一部分上形成掩模层。 在掩模层和高k栅极电介质层的暴露的第二部分上形成第一金属层之后，去除掩模层。 然后在第一金属层和高k栅极电介质层的第一部分上形成第二金属层。

公开(公告)号：US20050136677A1

公开(公告)日：2005-06-23

申请号：US10739173

申请日：2003-12-18

Applicant: Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

Inventor： Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Mark Doczy ,  Matthew Metz ,  Robert Chau

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/28185 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method for making a semiconductor device is described. That method comprises forming a dummy dielectric layer that is at least about 10 angstroms thick on a substrate, and forming a sacrificial layer on the dummy dielectric layer. After removing the sacrificial layer and the dummy dielectric layer to generate a trench that is positioned between first and second spacers, a gate dielectric layer is formed on the substrate at the bottom of the trench, and a metal layer is formed on the gate dielectric layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成至少约10埃厚的虚拟电介质层，并在虚拟电介质层上形成牺牲层。 在除去牺牲层和虚设电介质层以产生位于第一和第二间隔物之间​​的沟槽之后，在沟槽的底部的衬底上形成栅介质层，并且在栅介质层上形成金属层 。

公开(公告)号：US06869889B1

公开(公告)日：2005-03-22

申请号：US10819789

申请日：2004-04-07

Applicant: Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Terence Bacuita ,  Robert S. Chau

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Terence Bacuita ,  Robert S. Chau

IPC: H01L21/302 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L21/82345 ,  H01L21/32134 ,  H01L29/4966

Abstract: A metal carbide film may be etched in an etchant bath using sonication. The sonication may drive the reaction and, particularly, the gaseous byproducts in the form of carbon dioxide. Thus, the use of sonication invokes a favorable equilibrium to pattern metal carbide films, for example, for use as metal gate electrodes.

Abstract translation: 可以使用超声处理在蚀刻液浴中蚀刻金属碳化物膜。 超声处理可以驱动反应，特别是二氧化碳形式的气态副产物。 因此，使用超声处理引起对图案金属碳化物膜的有利平衡，例如用作金属栅电极。